8  * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0	0x0
28 #define FABRIC_EN_CFG_STATUS_0_0		0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0		0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0		0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0			0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0		0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0		0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0		0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0	0x20c
38 #define FABRIC_MN_MASTER_LOG_ERR_STATUS_0	0x300
39 #define FABRIC_MN_MASTER_LOG_ADDR_LOW_0		0x304
40 #define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0	0x308
41 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0	0x30c
42 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0	0x310
43 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0	0x314
44 #define FABRIC_MN_MASTER_LOG_USER_BITS0_0	0x318
46 #define AXI_SLV_TIMEOUT_STATUS_0_0		0x8
47 #define APB_BLOCK_TMO_STATUS_0			0xc00
48 #define APB_BLOCK_NUM_TMO_OFFSET		0x20
53 #define FAB_EM_EL_FALCONSEC		GENMASK(1, 0)
56 #define FAB_EM_EL_SLAVEID		GENMASK(7, 0)
58 #define FAB_EM_EL_ACCESSID		GENMASK(7, 0)
65 #define FAB_EM_EL_ACCESSTYPE		GENMASK(0, 0)
71 #define CCPLEX_MSTRID			0x1
72 #define FIREWALL_APERTURE_SZ		0x10000
74 #define WEN				0x20000
180 	writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);  in tegra234_cbb_fault_enable()
188 	writel(0x3f, priv->mon + FABRIC_MN_MASTER_ERR_STATUS_0);  in tegra234_cbb_error_clear()
207 	writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);  in tegra234_cbb_mask_serror()
228 	unsigned int block = 0;  in tegra234_cbb_lookup_apbslv()
238 		if (status & BIT(0)) {  in tegra234_cbb_lookup_apbslv()
239 			u32 timeout, clients, client = 0;  in tegra234_cbb_lookup_apbslv()
246 				if (timeout & BIT(0)) {  in tegra234_cbb_lookup_apbslv()
247 					if (clients != 0xffffffff)  in tegra234_cbb_lookup_apbslv()
311 	unsigned int type = 0;  in tegra234_cbb_print_error()
323 		if (status & 0x1)  in tegra234_cbb_print_error()
331 	type = 0;  in tegra234_cbb_print_error()
340 		if (overflow & 0x1)  in tegra234_cbb_print_error()
374 			if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))  in print_errlog_err()
458 	if (status == 0xffffffff) {  in print_errmonX_info()
473 	cbb->type = 0;  in print_errmonX_info()
476 		if (error & BIT(0)) {  in print_errmonX_info()
496 	return 0;  in print_errmonX_info()
501 	unsigned int index = 0;  in print_err_notifier()
509 		if (status & BIT(0)) {  in print_err_notifier()
536 	return 0;  in print_err_notifier()
544 	int err = 0;  in tegra234_cbb_debugfs_show()
583 			tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n",  in tegra234_cbb_isr()
592 			 * If illegal request is from CCPLEX(id:0x1) master then call WARN()  in tegra234_cbb_isr()
616 		int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,  in tegra234_cbb_interrupt_enable()
625 	return 0;  in tegra234_cbb_interrupt_enable()
645 	[0x00] = "TZ",
646 	[0x01] = "CCPLEX",
647 	[0x02] = "CCPMU",
648 	[0x03] = "BPMP_FW",
649 	[0x04] = "AON",
650 	[0x05] = "SCE",
651 	[0x06] = "GPCDMA_P",
652 	[0x07] = "TSECA_NONSECURE",
653 	[0x08] = "TSECA_LIGHTSECURE",
654 	[0x09] = "TSECA_HEAVYSECURE",
655 	[0x0a] = "CORESIGHT",
656 	[0x0b] = "APE",
657 	[0x0c] = "PEATRANS",
658 	[0x0d] = "JTAGM_DFT",
659 	[0x0e] = "RCE",
660 	[0x0f] = "DCE",
661 	[0x10] = "PSC_FW_USER",
662 	[0x11] = "PSC_FW_SUPERVISOR",
663 	[0x12] = "PSC_FW_MACHINE",
664 	[0x13] = "PSC_BOOT",
665 	[0x14] = "BPMP_BOOT",
666 	[0x15] = "NVDEC_NONSECURE",
667 	[0x16] = "NVDEC_LIGHTSECURE",
668 	[0x17] = "NVDEC_HEAVYSECURE",
669 	[0x18] = "CBB_INTERNAL",
670 	[0x19] = "RSVD"
696 	{ "AXI2APB", 0x00000 },
697 	{ "AST",     0x14000 },
698 	{ "CBB",     0x15000 },
699 	{ "CPU",     0x16000 },
709 	.notifier_offset = 0x17000,
710 	.firewall_base = 0x30000,
711 	.firewall_ctl = 0x8d0,
712 	.firewall_wr_ctl = 0x8c8,
716 	{ "AXI2APB", 0x00000 },
717 	{ "AST0",    0x15000 },
718 	{ "AST1",    0x16000 },
719 	{ "CBB",     0x17000 },
720 	{ "CPU",     0x18000 },
730 	.notifier_offset = 0x19000,
731 	.firewall_base = 0x30000,
732 	.firewall_ctl = 0x8f0,
733 	.firewall_wr_ctl = 0x8e8,
737 	{ "AON",        0x40000 },
738 	{ "BPMP",       0x41000 },
739 	{ "CBB",        0x42000 },
740 	{ "HOST1X",     0x43000 },
741 	{ "STM",        0x44000 },
742 	{ "FSI",        0x45000 },
743 	{ "PSC",        0x46000 },
744 	{ "PCIE_C1",    0x47000 },
745 	{ "PCIE_C2",    0x48000 },
746 	{ "PCIE_C3",    0x49000 },
747 	{ "PCIE_C0",    0x4a000 },
748 	{ "PCIE_C4",    0x4b000 },
749 	{ "GPU",        0x4c000 },
750 	{ "SMMU0",      0x4d000 },
751 	{ "SMMU1",      0x4e000 },
752 	{ "SMMU2",      0x4f000 },
753 	{ "SMMU3",      0x50000 },
754 	{ "SMMU4",      0x51000 },
755 	{ "PCIE_C10",   0x52000 },
756 	{ "PCIE_C7",    0x53000 },
757 	{ "PCIE_C8",    0x54000 },
758 	{ "PCIE_C9",    0x55000 },
759 	{ "PCIE_C5",    0x56000 },
760 	{ "PCIE_C6",    0x57000 },
761 	{ "DCE",        0x58000 },
762 	{ "RCE",        0x59000 },
763 	{ "SCE",        0x5a000 },
764 	{ "AXI2APB_1",  0x70000 },
765 	{ "AXI2APB_10", 0x71000 },
766 	{ "AXI2APB_11", 0x72000 },
767 	{ "AXI2APB_12", 0x73000 },
768 	{ "AXI2APB_13", 0x74000 },
769 	{ "AXI2APB_14", 0x75000 },
770 	{ "AXI2APB_15", 0x76000 },
771 	{ "AXI2APB_16", 0x77000 },
772 	{ "AXI2APB_17", 0x78000 },
773 	{ "AXI2APB_18", 0x79000 },
774 	{ "AXI2APB_19", 0x7a000 },
775 	{ "AXI2APB_2",  0x7b000 },
776 	{ "AXI2APB_20", 0x7c000 },
777 	{ "AXI2APB_21", 0x7d000 },
778 	{ "AXI2APB_22", 0x7e000 },
779 	{ "AXI2APB_23", 0x7f000 },
780 	{ "AXI2APB_25", 0x80000 },
781 	{ "AXI2APB_26", 0x81000 },
782 	{ "AXI2APB_27", 0x82000 },
783 	{ "AXI2APB_28", 0x83000 },
784 	{ "AXI2APB_29", 0x84000 },
785 	{ "AXI2APB_30", 0x85000 },
786 	{ "AXI2APB_31", 0x86000 },
787 	{ "AXI2APB_32", 0x87000 },
788 	{ "AXI2APB_33", 0x88000 },
789 	{ "AXI2APB_34", 0x89000 },
790 	{ "AXI2APB_35", 0x92000 },
791 	{ "AXI2APB_4",  0x8b000 },
792 	{ "AXI2APB_5",  0x8c000 },
793 	{ "AXI2APB_6",  0x8d000 },
794 	{ "AXI2APB_7",  0x8e000 },
795 	{ "AXI2APB_8",  0x8f000 },
796 	{ "AXI2APB_9",  0x90000 },
797 	{ "AXI2APB_3",  0x91000 },
807 	.notifier_offset = 0x60000,
808 	.off_mask_erd = 0x3a004,
809 	.firewall_base = 0x10000,
810 	.firewall_ctl = 0x23f0,
811 	.firewall_wr_ctl = 0x23e8,
815 	{ "AXI2APB", 0x00000 },
816 	{ "AST0",    0x15000 },
817 	{ "AST1",    0x16000 },
818 	{ "CBB",     0x17000 },
819 	{ "RSVD",    0x00000 },
820 	{ "CPU",     0x18000 },
830 	.notifier_offset = 0x19000,
831 	.firewall_base = 0x30000,
832 	.firewall_ctl = 0x290,
833 	.firewall_wr_ctl = 0x288,
843 	.notifier_offset = 0x19000,
844 	.firewall_base = 0x30000,
845 	.firewall_ctl = 0x290,
846 	.firewall_wr_ctl = 0x288,
856 	.notifier_offset = 0x19000,
857 	.firewall_base = 0x30000,
858 	.firewall_ctl = 0x290,
859 	.firewall_wr_ctl = 0x288,
863 	[0x0] = "TZ",
864 	[0x1] = "CCPLEX",
865 	[0x2] = "CCPMU",
866 	[0x3] = "BPMP_FW",
867 	[0x4] = "PSC_FW_USER",
868 	[0x5] = "PSC_FW_SUPERVISOR",
869 	[0x6] = "PSC_FW_MACHINE",
870 	[0x7] = "PSC_BOOT",
871 	[0x8] = "BPMP_BOOT",
872 	[0x9] = "JTAGM_DFT",
873 	[0xa] = "CORESIGHT",
874 	[0xb] = "GPU",
875 	[0xc] = "PEATRANS",
876 	[0xd ... 0x3f] = "RSVD"
972 	{ "RSVD",       0x00000 },
973 	{ "PCIE_C8",    0x51000 },
974 	{ "PCIE_C9",    0x52000 },
975 	{ "RSVD",       0x00000 },
976 	{ "RSVD",       0x00000 },
977 	{ "RSVD",       0x00000 },
978 	{ "RSVD",       0x00000 },
979 	{ "RSVD",       0x00000 },
980 	{ "RSVD",       0x00000 },
981 	{ "RSVD",       0x00000 },
982 	{ "RSVD",       0x00000 },
983 	{ "AON",        0x5b000 },
984 	{ "BPMP",       0x5c000 },
985 	{ "RSVD",       0x00000 },
986 	{ "RSVD",       0x00000 },
987 	{ "PSC",        0x5d000 },
988 	{ "STM",        0x5e000 },
989 	{ "AXI2APB_1",  0x70000 },
990 	{ "AXI2APB_10", 0x71000 },
991 	{ "AXI2APB_11", 0x72000 },
992 	{ "AXI2APB_12", 0x73000 },
993 	{ "AXI2APB_13", 0x74000 },
994 	{ "AXI2APB_14", 0x75000 },
995 	{ "AXI2APB_15", 0x76000 },
996 	{ "AXI2APB_16", 0x77000 },
997 	{ "AXI2APB_17", 0x78000 },
998 	{ "AXI2APB_18", 0x79000 },
999 	{ "AXI2APB_19", 0x7a000 },
1000 	{ "AXI2APB_2",  0x7b000 },
1001 	{ "AXI2APB_20", 0x7c000 },
1002 	{ "AXI2APB_4",  0x87000 },
1003 	{ "AXI2APB_5",  0x88000 },
1004 	{ "AXI2APB_6",  0x89000 },
1005 	{ "AXI2APB_7",  0x8a000 },
1006 	{ "AXI2APB_8",  0x8b000 },
1007 	{ "AXI2APB_9",  0x8c000 },
1008 	{ "AXI2APB_3",  0x8d000 },
1009 	{ "AXI2APB_21", 0x7d000 },
1010 	{ "AXI2APB_22", 0x7e000 },
1011 	{ "AXI2APB_23", 0x7f000 },
1012 	{ "AXI2APB_24", 0x80000 },
1013 	{ "AXI2APB_25", 0x81000 },
1014 	{ "AXI2APB_26", 0x82000 },
1015 	{ "AXI2APB_27", 0x83000 },
1016 	{ "AXI2APB_28", 0x84000 },
1017 	{ "PCIE_C4",    0x53000 },
1018 	{ "PCIE_C5",    0x54000 },
1019 	{ "PCIE_C6",    0x55000 },
1020 	{ "PCIE_C7",    0x56000 },
1021 	{ "PCIE_C2",    0x57000 },
1022 	{ "PCIE_C3",    0x58000 },
1023 	{ "PCIE_C0",    0x59000 },
1024 	{ "PCIE_C1",    0x5a000 },
1025 	{ "CCPLEX",     0x50000 },
1026 	{ "AXI2APB_29", 0x85000 },
1027 	{ "AXI2APB_30", 0x86000 },
1028 	{ "CBB_CENTRAL", 0x00000 },
1029 	{ "AXI2APB_31", 0x8E000 },
1030 	{ "AXI2APB_32", 0x8F000 },
1040 	.notifier_offset = 0x60000,
1041 	.off_mask_erd = 0x40004,
1042 	.firewall_base = 0x20000,
1043 	.firewall_ctl = 0x2370,
1044 	.firewall_wr_ctl = 0x2368,
1048 	{ "RSVD",    0x00000 },
1049 	{ "RSVD",    0x00000 },
1050 	{ "RSVD",    0x00000 },
1051 	{ "CBB",     0x15000 },
1052 	{ "CPU",     0x16000 },
1053 	{ "AXI2APB", 0x00000 },
1054 	{ "DBB0",    0x17000 },
1055 	{ "DBB1",    0x18000 },
1065 	.notifier_offset = 0x19000,
1066 	.firewall_base = 0x30000,
1067 	.firewall_ctl = 0x8f0,
1068 	.firewall_wr_ctl = 0x8e8,
1117 	unsigned long flags = 0;  in tegra234_cbb_probe()
1143 	cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);  in tegra234_cbb_probe()
1159 		return 0;  in tegra234_cbb_probe()
1181 	return 0;  in tegra234_cbb_resume_noirq()