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Searched +full:0 +full:x16080 (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8953.yaml91 reg = <0x580000 0x16080>;
/linux/arch/powerpc/perf/
H A Dpower7-pmu.c19 #define PM_PMC_MSK 0xf
22 #define PM_UNIT_MSK 0xf
25 #define PM_COMBINE_MSKS 0x800
28 #define PM_PMCSEL_MSK 0xff
37 #define MMCR1_TTMSEL_MSK 0xf
47 #define MMCR1_PMC4SEL_SH 0
49 #define MMCR1_PMCSEL_MSK 0xff
72 * 15: NC error 0x8000
73 * 12-14: number of events needing PMC1-4 0x7000
76 * 11: P6 error 0x800
[all …]
H A Dpower7-events-list.h8 EVENT(PM_IC_DEMAND_L2_BR_ALL, 0x04898)
9 EVENT(PM_GCT_UTIL_7_TO_10_SLOTS, 0x020a0)
10 EVENT(PM_PMC2_SAVED, 0x10022)
11 EVENT(PM_CMPLU_STALL_DFU, 0x2003c)
12 EVENT(PM_VSU0_16FLOP, 0x0a0a4)
13 EVENT(PM_MRK_LSU_DERAT_MISS, 0x3d05a)
14 EVENT(PM_MRK_ST_CMPL, 0x10034)
15 EVENT(PM_NEST_PAIR3_ADD, 0x40881)
16 EVENT(PM_L2_ST_DISP, 0x46180)
17 EVENT(PM_L2_CASTOUT_MOD, 0x16180)
[all …]
/linux/drivers/interconnect/qcom/
H A Dmsm8953.c104 .qos.prio_level = 0,
105 .qos.areq_prio = 0,
106 .qos.qos_port = 0,
122 .qos.prio_level = 0,
123 .qos.areq_prio = 0,
140 .qos.prio_level = 0,
141 .qos.areq_prio = 0,
158 .qos.prio_level = 0,
159 .qos.areq_prio = 0,
202 .slv_rpm_id = 0,
[all …]
H A Dmsm8937.c105 .mas_rpm_id = 0,
109 .qos.areq_prio = 0,
110 .qos.prio_level = 0,
111 .qos.qos_port = 0,
129 .qos.areq_prio = 0,
130 .qos.prio_level = 0,
149 .qos.areq_prio = 0,
150 .qos.prio_level = 0,
169 .qos.areq_prio = 0,
170 .qos.prio_level = 0,
[all …]
H A Dsa8775p.c217 .port_offsets = { 0x11000 },
220 .urg_fwd = 0,
232 .port_offsets = { 0x12000 },
235 .urg_fwd = 0,
247 .port_offsets = { 0x13000 },
250 .urg_fwd = 0,
262 .port_offsets = { 0x14000 },
265 .urg_fwd = 0,
277 .port_offsets = { 0x15000 },
280 .urg_fwd = 0,
[all …]
H A Dqcs8300.c191 .port_offsets = { 0x11000 },
194 .urg_fwd = 0,
206 .port_offsets = { 0x12000 },
209 .urg_fwd = 0,
221 .port_offsets = { 0x14000 },
224 .urg_fwd = 0,
236 .port_offsets = { 0x15000 },
239 .urg_fwd = 0,
251 .port_offsets = { 0x16000 },
254 .urg_fwd = 0,
[all …]
H A Dsc8280xp.c220 .port_offsets = { 0x5000 },
233 .port_offsets = { 0x6000 },
246 .port_offsets = { 0xc000 },
267 .port_offsets = { 0x8000 },
281 .port_offsets = { 0xd000 },
294 .port_offsets = { 0x7000 },
307 .port_offsets = { 0x9000 },
320 .port_offsets = { 0xb000 },
333 .port_offsets = { 0xa000 },
346 .port_offsets = { 0xe000 },
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmonaco.dtsi35 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0 0x0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
105 reg = <0x0 0x200>;
131 reg = <0x0 0x300>;
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]