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12

/linux/arch/arc/boot/dts/
H A Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
H A Dp1022si-post.dtsi43 interrupts = <19 2 0 0>,
44 <16 2 0 0>;
47 /* controller at 0x9000 */
53 bus-range = <0 255>;
55 interrupts = <16 2 0 0>;
57 pcie@0 {
58 reg = <0 0 0 0 0>;
63 interrupts = <16 2 0 0>;
64 interrupt-map-mask = <0xf800 0 0 7>;
66 /* IDSEL 0x0 */
[all …]
/linux/drivers/net/wireless/ti/wl18xx/
H A Dreg.h11 #define WL18XX_REGISTERS_BASE 0x00800000
12 #define WL18XX_CODE_BASE 0x00000000
13 #define WL18XX_DATA_BASE 0x00400000
14 #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
15 #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
16 #define WL18XX_PHY_BASE 0x00900000
17 #define WL18XX_TOP_OCP_BASE 0x00A00000
18 #define WL18XX_PACKET_RAM_BASE 0x00B00000
19 #define WL18XX_HOST_BASE 0x00C00000
21 #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-ts4800.dts22 reg = <0x90000000 0x10000000>;
38 pinctrl-0 = <&pinctrl_enable_lcd>;
48 pwms = <&pwm1 0 78770 0>;
49 brightness-levels = <0 150 200 255>;
58 pinctrl-0 = <&pinctrl_lcd>;
69 vback-porch = <0>;
70 vfront-porch = <0>;
85 pinctrl-0 = <&pinctrl_esdhc1>;
86 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
93 pinctrl-0 = <&pinctrl_fec>;
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0 0>;
29 reg = <0 1>;
36 reg = <0 2>;
43 reg = <0 3>;
69 reg = <0 0x8100000 0 0x40000>;
70 record-size = <0x8000>;
71 console-size = <0x20000>;
92 reg = <0 0xc0010000 0 0x10000>;
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_device.c52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_12_2_glymur.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x1000,
35 .base = 0x16000, .len = 0x1000,
39 .base = 0x17000, .len = 0x1000,
43 .base = 0x18000, .len = 0x1000,
47 .base = 0x19000, .len = 0x1000,
51 .base = 0x1a000, .len = 0x1000,
55 .base = 0x1b000, .len = 0x1000,
[all …]
/linux/drivers/interconnect/qcom/
H A Dsc7280.c27 .port_offsets = { 0x7000 },
29 .urg_fwd = 0,
42 .port_offsets = { 0x11000 },
44 .urg_fwd = 0,
57 .port_offsets = { 0x8000 },
59 .urg_fwd = 0,
81 .port_offsets = { 0xc000 },
83 .urg_fwd = 0,
96 .port_offsets = { 0xe000 },
98 .urg_fwd = 0,
[all …]
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg.dtsi24 tdmif_a: audio-controller-0 {
26 #sound-dai-cells = <0>;
37 #sound-dai-cells = <0>;
48 #sound-dai-cells = <0>;
67 #address-cells = <0x2>;
68 #size-cells = <0x0>;
70 cpu0: cpu@0 {
73 reg = <0x0 0x0>;
76 clocks = <&scpi_dvfs 0>;
84 reg = <0x0 0x1>;
[all …]
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_type.h16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
35 #define WX_MIS_RST_SW_RST BIT(0)
[all …]
/linux/drivers/clk/qcom/
H A Dcamcc-sa8775p.c48 { 249600000, 2020000000, 0 },
52 { 864000000, 1056000000, 0 },
56 .l = 0x3e,
57 .alpha = 0x8000,
58 .config_ctl_val = 0x20485699,
59 .config_ctl_hi_val = 0x00182261,
60 .config_ctl_hi1_val = 0x32aa299c,
61 .user_ctl_val = 0x00008400,
62 .user_ctl_hi_val = 0x00400805,
66 .offset = 0x0,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8937.dtsi22 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0x0>;
47 cache-size = <0x80000>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
[all …]
H A Dmsm8976.dtsi27 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
38 reg = <0x0>;
49 reg = <0x1>;
60 reg = <0x2>;
71 reg = <0x3>;
82 reg = <0x100>;
93 reg = <0x101>;
104 reg = <0x102>;
[all …]

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