/linux/drivers/clk/renesas/ |
H A D | r8a774e1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), 117 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a774a1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), 116 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a7795-cpg-mssr.c | 81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), 105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), 106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), 107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), 108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), 109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), 110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), 111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), 121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a7796-cpg-mssr.c | 83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 106 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), 107 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), 108 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), 109 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), 110 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), 111 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), 112 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), 113 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), 123 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a774b1-cpg-mssr.c | 97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), 98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), 99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), 100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), 101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), 102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), 103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), 104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), 113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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H A D | r8a77965-cpg-mssr.c | 101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074), 102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078), 103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268), 104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c), 105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074), 106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078), 107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), 108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), 118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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/linux/drivers/media/usb/gspca/ |
H A D | konica.c | 29 #define WHITEBAL_REG 0x01 30 #define BRIGHTNESS_REG 0x02 31 #define SHARPNESS_REG 0x03 32 #define CONTRAST_REG 0x04 33 #define SATURATION_REG 0x05 44 0x00 -> 176x144, cropped 45 0x01 -> 176x144, cropped 46 0x02 -> 176x144, cropped 47 0x03 -> 176x144, cropped 48 0x04 -> 176x144, binned [all …]
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H A D | xirlink_cit.c | 29 module_param(ibm_netcam_pro, int, 0); 44 #define CIT_MODEL0 0 /* bcd version 0.01 cams ie the xvp-500 */ 125 {0, 0x0000, 0x010c}, 126 {0, 0x0006, 0x012c}, 127 {0, 0x0078, 0x012d}, 128 {0, 0x0046, 0x012f}, 129 {0, 0xd141, 0x0124}, 130 {0, 0x0000, 0x0127}, 131 {0, 0xfea8, 0x0124}, 132 {1, 0x0000, 0x0116}, [all …]
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/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 #define QSERDES_V4_TX_BIST_INVERT 0x004 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19 #define QSERDES_V4_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 #define QSERDES_V5_TX_BIST_INVERT 0x004 13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 #define QSERDES_V5_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v3.h | 11 #define QSERDES_V3_COM_ATB_SEL1 0x000 12 #define QSERDES_V3_COM_ATB_SEL2 0x004 13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008 14 #define QSERDES_V3_COM_BG_TIMER 0x00c 15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 18 #define QSERDES_V3_COM_SSC_PER1 0x01c 19 #define QSERDES_V3_COM_SSC_PER2 0x020 20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v5.h | 10 #define QSERDES_V5_COM_ATB_SEL1 0x000 11 #define QSERDES_V5_COM_ATB_SEL2 0x004 12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008 13 #define QSERDES_V5_COM_BG_TIMER 0x00c 14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_V5_COM_SSC_PER1 0x01c 18 #define QSERDES_V5_COM_SSC_PER2 0x020 19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 [all …]
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/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | st,stm32-rproc.yaml | 168 reg = <0x10000000 0x40000>, 169 <0x30000000 0x40000>, 170 <0x38000000 0x10000>; 174 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 182 reg = <0x10000000 0x40000>, 183 <0x30000000 0x40000>, 184 <0x38000000 0x10000>; 188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; [all …]
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/linux/drivers/clk/mstar/ |
H A D | clk-msc313-cpupll.c | 17 * 0x140 -- LPF low. Seems to store one half of the clock transition 18 * 0x144 / 19 * 0x148 -- LPF high. Seems to store one half of the clock transition 20 * 0x14c / 21 * 0x150 -- vendor code says "toggle lpf enable" 22 * 0x154 -- mu? 23 * 0x15c -- lpf_update_count? 24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? 25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to 27 * 0x174 -- Seems to be the PLL lock status bit [all …]
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/linux/drivers/hwtracing/coresight/ |
H A D | coresight-cti.h | 22 * 0x000 - 0x144: CTI programming and status 23 * 0xEDC - 0xEF8: CTI integration test. 24 * 0xF00 - 0xFFC: Coresight management registers. 27 #define CTICONTROL 0x000 28 #define CTIINTACK 0x010 29 #define CTIAPPSET 0x014 30 #define CTIAPPCLEAR 0x018 31 #define CTIAPPPULSE 0x01C 32 #define CTIINEN(n) (0x020 + (4 * n)) 33 #define CTIOUTEN(n) (0x0A0 + (4 * n)) [all …]
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/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/linux/drivers/clk/meson/ |
H A D | s4-peripherals.h | 10 #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 11 #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 12 #define CLKCTRL_RTC_CTRL 0x010 13 #define CLKCTRL_SYS_CLK_CTRL0 0x040 14 #define CLKCTRL_SYS_CLK_EN0_REG0 0x044 15 #define CLKCTRL_SYS_CLK_EN0_REG1 0x048 16 #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 17 #define CLKCTRL_SYS_CLK_EN0_REG3 0x050 18 #define CLKCTRL_CECA_CTRL0 0x088 19 #define CLKCTRL_CECA_CTRL1 0x08c [all …]
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H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40 20 #define HHI_GP0_PLL_CNTL2 0x44 21 #define HHI_GP0_PLL_CNTL3 0x48 22 #define HHI_GP0_PLL_CNTL4 0x4c 23 #define HHI_GP0_PLL_CNTL5 0x50 24 #define HHI_GP0_PLL_STS 0x54 25 #define HHI_GP0_PLL_CNTL1 0x58 26 #define HHI_HIFI_PLL_CNTL 0x80 27 #define HHI_HIFI_PLL_CNTL2 0x84 28 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/linux/arch/arm/mach-davinci/ |
H A D | clock.h | 13 #define PLLCTL 0x100 14 #define PLLCTL_PLLEN BIT(0) 21 #define PLLM 0x110 22 #define PLLM_PLLM_MASK 0xff 24 #define PREDIV 0x114 25 #define PLLDIV1 0x118 26 #define PLLDIV2 0x11c 27 #define PLLDIV3 0x120 28 #define POSTDIV 0x128 29 #define BPDIV 0x12c [all …]
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/linux/drivers/mmc/host/ |
H A D | sdhci-esdhc.h | 27 #define ESDHC_HOST_CONTROL_LE 0x20 34 #define ESDHC_PRSSTAT 0x24 35 #define ESDHC_CLOCK_GATE_OFF 0x00000080 36 #define ESDHC_CLOCK_STABLE 0x00000008 39 #define ESDHC_PROCTL 0x28 40 #define ESDHC_VOLT_SEL 0x00000400 41 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 42 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 43 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 44 #define ESDHC_HOST_CONTROL_RES 0x01 [all …]
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/linux/drivers/usb/fotg210/ |
H A D | fotg210-udc.h | 14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */ 15 #define FOTG210_GMIR 0xC4 16 #define GMIR_INT_POLARITY 0x8 /*Active High*/ 17 #define GMIR_MHC_INT 0x4 18 #define GMIR_MOTG_INT 0x2 19 #define GMIR_MDEV_INT 0x1 21 /* Device Main Control Register(0x100) */ 22 #define FOTG210_DMCR 0x100 29 #define DMCR_CAP_RMWAKUP (1 << 0) 31 /* Device Address Register(0x104) */ [all …]
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/linux/drivers/media/usb/gspca/stv06xx/ |
H A D | stv06xx.h | 25 #define STV_ISOC_ENDPOINT_ADDR 0x81 27 #define STV_R 0x0509 29 #define STV_REG23 0x0423 32 #define STV_I2C_PARTNER 0x1420 33 #define STV_I2C_VAL_REG_VAL_PAIRS_MIN1 0x1421 34 #define STV_I2C_READ_WRITE_TOGGLE 0x1422 35 #define STV_I2C_FLUSH 0x1423 36 #define STV_I2C_SUCC_READ_REG_VALS 0x1424 38 #define STV_ISO_ENABLE 0x1440 39 #define STV_SCAN_RATE 0x1443 [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/linux/drivers/net/wireless/marvell/mwifiex/ |
H A D | cfp.c | 28 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 }; 30 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24, 31 0xb0, 0x48, 0x60, 0x6c, 0 }; 33 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 34 0x0c, 0x12, 0x18, 0x24, 35 0x30, 0x48, 0x60, 0x6c, 0 }; 37 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24, 38 0xb0, 0x48, 0x60, 0x6c, 0 }; 39 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24, 40 0xb0, 0x48, 0x60, 0x6c, 0 }; [all …]
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