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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey-pinctrl.dtsi12 pinctrl-0 = <
22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
[all …]
/freebsd/sys/arm/ti/
H A Dti_spireg.h32 #define MCSPI_REVISION 0x0
34 #define MCSPI_REVISION_SCHEME_MSK 0x3
36 #define MCSPI_REVISION_FUNC_MSK 0xfff
38 #define MCSPI_REVISION_RTL_MSK 0x1f
40 #define MCSPI_REVISION_MAJOR_MSK 0x7
42 #define MCSPI_REVISION_CUSTOM_MSK 0x3
43 #define MCSPI_REVISION_MINOR_SHIFT 0
44 #define MCSPI_REVISION_MINOR_MSK 0x3f
45 #define MCSPI_SYSCONFIG 0x110
47 #define MCSPI_SYSSTATUS 0x114
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_eeprom.h13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
[all …]
/freebsd/sys/dev/xilinx/
H A Dxlnx_pcib.h36 #define XLNX_PCIE_VSEC 0x12c
37 #define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */
38 #define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */
39 #define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */
40 #define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */
41 #define IMR_LINK_DOWN (1 << 0)
44 #define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S)
59 #define XLNX_PCIE_BLR 0x140 /* Bus Location Register */
60 #define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */
62 #define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */
[all …]
/freebsd/cddl/contrib/opensolaris/cmd/lockstat/
H A Dlockstat.1250 .Bl -tag -width 0n
259 13750 33% 33% 0.00 72 vm_page_queue_free_mtx vm_page_free_toq+0x12e
260 13648 33% 66% 0.00 66 vm_page_queue_free_mtx vm_page_alloc+0x138
261 4023 10% 76% 0.00 51 vm_dom+0x80 vm_page_dequeue+0x68
262 2672 6% 82% 0.00 186 vm_dom+0x80 vm_page_enqueue+0x63
263 618 1% 84% 0.00 31 0xfffff8000cd83a88 qsyncvp+0x37
264 506 1% 85% 0.00 164 0xfffff8000cb3f098 vputx+0x5a
265 477 1% 86% 0.00 69 0xfffff8000c7eb180 uma_dbg_getslab+0x5b
266 288 1% 87% 0.00 77 0xfffff8000cd8b000 vn_finished_write+0x29
267 263 1% 88% 0.00 103 0xfffff8000cbad448 vinactive+0xdc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml112 reg = <0x32ec0000 0x138>;
135 reg = <0x5c 0x4>, <0x128 0x4>;
142 #size-cells = <0>;
144 port@0 {
145 reg = <0>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Domap4.h8 #define OMAP4_CLKCTRL_OFFSET 0x20
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dxilinx13 0 beshort 0x0009
14 >2 belong =0x0ff00ff0
15 >>&0 belong =0x0ff00ff0
16 >>>&0 byte =0x00
17 >>>>&1 beshort =0x0001
20 >>>>>>&0 pstring/H x - from %s
24 >>>>>>>>&0 pstring/H x - for %s
28 >>>>>>>>>>&0 pstring/H x - built %s
32 >>>>>>>>>>>>&0 pstring/H x \b(%s)
36 >>>>>>>>>>>>>>&0 belong x - data length %#x
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h7 #define ADF_C62X_SRAM_BAR 0
11 #define ADF_C62X_TX_RINGS_MASK 0xFF
15 #define ADF_C62X_ACCELERATORS_MASK 0x1F
16 #define ADF_C62X_ACCELENGINES_MASK 0x3FF
18 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
19 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
20 #define ADF_C62X_SMIA0_MASK 0xFFFF
21 #define ADF_C62X_SMIA1_MASK 0x1
22 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
27 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/freebsd/tools/test/stress2/misc/
H A Dsyzkaller46.sh5 # fault virtual address = 0x28
7 # instruction pointer = 0x20:0xffffffff81549dea
8 # stack pointer = 0x28:0xfffffe01d8689480
9 # frame pointer = 0x28:0xfffffe01d8689490
10 # code segment = base 0x0, limit 0xfffff, type 0x1b
11 # = DPL 0, pres 1, long 1, def32 0, gran 1
12 # processor eflags = interrupt enabled, resume, IOPL = 0
19 # db_trace_self_wrapper() at db_trace_self_wrapper+0xa5/frame 0xfffffe01d8688cb0
20 # kdb_backtrace() at kdb_backtrace+0xc9/frame 0xfffffe01d8688e10
21 # vpanic() at vpanic+0x248/frame 0xfffffe01d8688ef0
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h7 #define ADF_200XX_PMISC_BAR 0
10 #define ADF_200XX_TX_RINGS_MASK 0xFF
14 #define ADF_200XX_ACCELERATORS_MASK 0x7
15 #define ADF_200XX_ACCELENGINES_MASK 0x3F
17 #define ADF_200XX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_200XX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_200XX_SMIA0_MASK 0xFFFF
20 #define ADF_200XX_SMIA1_MASK 0x1
21 #define ADF_200XX_SOFTSTRAP_CSR_OFFSET 0x2EC
25 #define ADF_200XX_PFIEERRUNCSTSR 0x280
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h7 #define ADF_C3XXX_PMISC_BAR 0
10 #define ADF_C3XXX_TX_RINGS_MASK 0xFF
14 #define ADF_C3XXX_ACCELERATORS_MASK 0x7
15 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F
17 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_C3XXX_SMIA0_MASK 0xFFFF
20 #define ADF_C3XXX_SMIA1_MASK 0x1
21 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
26 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h7 #define ADF_DH895XCC_SRAM_BAR 0
11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF
12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
[all …]

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