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/linux/drivers/media/usb/gspca/
H A Dsn9c2028.c37 unsigned char to_read; /* length to read. 0 means no reply requested */
46 .priv = 0},
55 .priv = 0},
64 command[0], command[1], command[2], in sn9c2028_command()
69 usb_sndctrlpipe(gspca_dev->dev, 0), in sn9c2028_command()
72 2, 0, gspca_dev->usb_buf, 6, 500); in sn9c2028_command()
73 if (rc < 0) { in sn9c2028_command()
75 gspca_dev->usb_buf[0], rc); in sn9c2028_command()
79 return 0; in sn9c2028_command()
87 usb_rcvctrlpipe(gspca_dev->dev, 0), in sn9c2028_read1()
[all …]
H A Dconex.c53 .priv = 0},
69 usb_rcvctrlpipe(dev, 0), in reg_r()
70 0, in reg_r()
72 0, in reg_r()
76 index, gspca_dev->usb_buf[0]); in reg_r()
86 gspca_dev->usb_buf[0] = val; in reg_w_val()
88 usb_sndctrlpipe(dev, 0), in reg_w_val()
89 0, in reg_w_val()
91 0, in reg_w_val()
111 usb_sndctrlpipe(dev, 0), in reg_w()
[all …]
H A Dov534_9.c20 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
21 #define OV534_REG_SUBADDR 0xf2
22 #define OV534_REG_WRITE 0xf3
23 #define OV534_REG_READ 0xf4
24 #define OV534_REG_OPERATION 0xf5
25 #define OV534_REG_STATUS 0xf6
27 #define OV534_OP_WRITE_3 0x37
28 #define OV534_OP_WRITE_2 0x33
29 #define OV534_OP_READ_2 0xf9
54 #define QVGA_MODE 0
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-jerry.dts25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
45 #size-cells = <0>;
52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192c.c21 .reg_0e00 = 0x07090c0c,
22 .reg_0e04 = 0x01020405,
23 .reg_0e08 = 0x00000000,
24 .reg_086c = 0x00000000,
26 .reg_0e10 = 0x0b0c0c0e,
27 .reg_0e14 = 0x01030506,
28 .reg_0e18 = 0x0b0c0d0e,
29 .reg_0e1c = 0x01030509,
31 .reg_0830 = 0x07090c0c,
32 .reg_0834 = 0x01020405,
[all …]
H A D8723a.c20 .reg_0e00 = 0x0a0c0c0c,
21 .reg_0e04 = 0x02040608,
22 .reg_0e08 = 0x00000000,
23 .reg_086c = 0x00000000,
25 .reg_0e10 = 0x0a0c0d0e,
26 .reg_0e14 = 0x02040608,
27 .reg_0e18 = 0x0a0c0d0e,
28 .reg_0e1c = 0x02040608,
30 .reg_0830 = 0x0a0c0c0c,
31 .reg_0834 = 0x02040608,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-rve-gateway.dts17 #clock-cells = <0>;
24 pinctrl-0 = <&pinctrl_gpio_keys>;
44 pinctrl-0 = <&pinctrl_lcd>;
70 pinctrl-0 = <&pinctrl_rotary>;
73 linux,axis = <0>; /* REL_X */
82 duart1: serial@0 {
84 reg = <0>;
99 /delete-node/ touchscreen@0;
104 pinctrl-0 = <&pinctrl_ecspi2>;
110 duart2: serial@0 {
[all …]
/linux/drivers/video/backlight/
H A Dlms283gf05.c33 { 0x07, 0x0000, 0 },
34 { 0x13, 0x0000, 10 },
36 { 0x11, 0x3004, 0 },
37 { 0x14, 0x200F, 0 },
38 { 0x10, 0x1a20, 0 },
39 { 0x13, 0x0040, 50 },
41 { 0x13, 0x0060, 0 },
42 { 0x13, 0x0070, 200 },
44 { 0x01, 0x0127, 0 },
45 { 0x02, 0x0700, 0 },
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
H A Docteon_68xx.dts16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/Documentation/devicetree/bindings/power/supply/
H A Dqcom,pm8916-lbc.yaml96 #size-cells = <0>;
100 reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
103 interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
104 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
105 <0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
106 <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
107 <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
108 <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
109 <0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
110 <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/
H A Divsrcid_vislands30.h30 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
31 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
33 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
34 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
36 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
37 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
39 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
40 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
42 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
43 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
[all …]
/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_al7230b.c15 RF_CHANNEL( 1) = { 0x09ec00, 0x8cccc8 },
16 RF_CHANNEL( 2) = { 0x09ec00, 0x8cccd8 },
17 RF_CHANNEL( 3) = { 0x09ec00, 0x8cccc0 },
18 RF_CHANNEL( 4) = { 0x09ec00, 0x8cccd0 },
19 RF_CHANNEL( 5) = { 0x05ec00, 0x8cccc8 },
20 RF_CHANNEL( 6) = { 0x05ec00, 0x8cccd8 },
21 RF_CHANNEL( 7) = { 0x05ec00, 0x8cccc0 },
22 RF_CHANNEL( 8) = { 0x05ec00, 0x8cccd0 },
23 RF_CHANNEL( 9) = { 0x0dec00, 0x8cccc8 },
24 RF_CHANNEL(10) = { 0x0dec00, 0x8cccd8 },
[all …]
/linux/lib/crypto/
H A Dcurve25519-fiat32.c18 * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77
41 h[0] = a0&((1<<26)-1); /* 26 used, 32-26 left. 26 */ in fe_frombytes_impl()
104 t = -!!t; /* all set if nonzero, 0 if 0 */ in cmovznz32()
119 { const u32 x2 = in1[0]; in fe_freeze()
120 { u32 x20; u8/*bool*/ x21 = subborrow_u26(0x0, x2, 0x3ffffed, &x20); in fe_freeze()
121 { u32 x23; u8/*bool*/ x24 = subborrow_u25(x21, x4, 0x1ffffff, &x23); in fe_freeze()
122 { u32 x26; u8/*bool*/ x27 = subborrow_u26(x24, x6, 0x3ffffff, &x26); in fe_freeze()
123 { u32 x29; u8/*bool*/ x30 = subborrow_u25(x27, x8, 0x1ffffff, &x29); in fe_freeze()
124 { u32 x32; u8/*bool*/ x33 = subborrow_u26(x30, x10, 0x3ffffff, &x32); in fe_freeze()
125 { u32 x35; u8/*bool*/ x36 = subborrow_u25(x33, x12, 0x1ffffff, &x35); in fe_freeze()
[all …]
/linux/arch/x86/kernel/cpu/microcode/
H A Damd_shas.c3 { 0x8001227, {
4 0x99,0xc0,0x9b,0x2b,0xcc,0x9f,0x52,0x1b,
5 0x1a,0x5f,0x1d,0x83,0xa1,0x6c,0xc4,0x46,
6 0xe2,0x6c,0xda,0x73,0xfb,0x2d,0x23,0xa8,
7 0x77,0xdc,0x15,0x31,0x33,0x4a,0x46,0x18,
10 { 0x8001250, {
11 0xc0,0x0b,0x6b,0x19,0xfd,0x5c,0x39,0x60,
12 0xd5,0xc3,0x57,0x46,0x54,0xe4,0xd1,0xaa,
13 0xa8,0xf7,0x1f,0xa8,0x6a,0x60,0x3e,0xe3,
14 0x27,0x39,0x8e,0x53,0x30,0xf8,0x49,0x19,
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-timon.c17 number. An alternate of 0 means that the mode is unavailable.
39 {1, 140, 0, {0x05, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x8C, 0xFC, 0x80, 0x02}},
40 {1, 140, 0, {0x05, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x8C, 0xFC, 0x80, 0x02}},
41 {1, 140, 0, {0x05, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x8C, 0xFC, 0x80, 0x02}},
42 {1, 140, 0, {0x05, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x8C, 0xFC, 0x80, 0x02}},
46 {2, 280, 0, {0x04, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x18, 0xA9, 0x80, 0x02}},
47 {2, 280, 0, {0x04, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x18, 0xA9, 0x80, 0x02}},
48 {2, 280, 0, {0x04, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x18, 0xA9, 0x80, 0x02}},
49 {2, 280, 0, {0x04, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x18, 0xA9, 0x80, 0x02}},
53 {3, 410, 0, {0x03, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x9A, 0x71, 0x80, 0x02}},
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-sitronix-st7703.c29 #define ST7703_CMD_ALL_PIXEL_OFF 0x22
30 #define ST7703_CMD_ALL_PIXEL_ON 0x23
31 #define ST7703_CMD_SETAPID 0xB1
32 #define ST7703_CMD_SETDISP 0xB2
33 #define ST7703_CMD_SETRGBIF 0xB3
34 #define ST7703_CMD_SETCYC 0xB4
35 #define ST7703_CMD_SETBGP 0xB5
36 #define ST7703_CMD_SETVCOM 0xB6
37 #define ST7703_CMD_SETOTP 0xB7
38 #define ST7703_CMD_SETPOWER_EXT 0xB8
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpm8916.dtsi17 hysteresis = <0>;
23 hysteresis = <0>;
29 hysteresis = <0>;
38 pm8916_0: pmic@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
47 mode-bootloader = <0x2>;
48 mode-recovery = <0x1>;
52 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
/linux/drivers/acpi/pmic/
H A Dintel_pmic_xpower.c16 #define XPOWER_GPADC_LOW 0x5b
17 #define XPOWER_GPI1_CTRL 0x92
19 #define GPI1_LDO_MASK GENMASK(2, 0)
20 #define GPI1_LDO_ON (3 << 0)
21 #define GPI1_LDO_OFF (4 << 0)
23 #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0)
24 #define AXP288_ADC_TS_CURRENT_OFF (0 << 0)
25 #define AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING (1 << 0)
26 #define AXP288_ADC_TS_CURRENT_ON_ONDEMAND (2 << 0)
27 #define AXP288_ADC_TS_CURRENT_ON (3 << 0)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_14_0_2_sh_mask.h30 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
31 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
32 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
33 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
34 …ON_CUR_TMP__REMOTE_TJ_SEL__SHIFT 0xd
35 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
36 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
37 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
38 …N_CUR_TMP__MCM_EN__SHIFT 0x14
39 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
/linux/crypto/
H A Dhkdf.c41 * Returns 0 on success with the pseudorandom key stored in @prk,
71 * Returns 0 on success with output keying material stored in @okm,
90 for (i = 0; i < okmlen; i += hashlen) { in hkdf_expand()
122 err = 0; in hkdf_expand()
172 "\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
205 .salt_size = 0,
207 .info_size = 0,
213 "\x9d\x20\x13\x95\xfa\xa4\xb6\x1a\x96\xc8",
239 .info_size = 0,
240 .prk = "\xaa\x84\x1e\x1f\x35\x74\xf3\x2d\x13\xfb\xa8\x00\x5f\xcd\x9b\x8d"
[all …]

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