Home
last modified time | relevance | path

Searched +full:0 +full:x12 (Results 1 – 25 of 1059) sorted by relevance

12345678910>>...43

/linux/tools/perf/arch/x86/tests/
H A Dinsn-x86-dat-32.c8 {{0x0f, 0x31, }, 2, 0, "", "",
9 "0f 31 \trdtsc ",},
10 {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
12 {{0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
13 "62 81 78 56 34 12 \tbound %eax,0x12345678(%ecx)",},
14 {{0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
15 "62 88 78 56 34 12 \tbound %ecx,0x12345678(%eax)",},
16 {{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
17 "62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",},
18 {{0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
[all …]
H A Dinsn-x86-dat-64.c8 {{0x0f, 0x31, }, 2, 0, "", "",
9 "0f 31 \trdtsc ",},
10 {{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
12 {{0x48, 0x0f, 0x41, 0xd8, }, 4, 0, "", "",
13 "48 0f 41 d8 \tcmovno %rax,%rbx",},
14 {{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
15 "48 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%rcx",},
16 {{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
17 "66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%cx",},
18 {{0x48, 0x0f, 0x44, 0xd8, }, 4, 0, "", "",
[all …]
H A Dinsn-x86-dat-src.c32 asm volatile("cmovno 0x12345678(%rax),%rcx"); in main()
33 asm volatile("cmovno 0x12345678(%rax),%cx"); in main()
36 asm volatile("cmove 0x12345678(%rax),%rcx"); in main()
37 asm volatile("cmove 0x12345678(%rax),%cx"); in main()
39 asm volatile("seto 0x12345678(%rax)"); in main()
40 asm volatile("setno 0x12345678(%rax)"); in main()
41 asm volatile("setb 0x12345678(%rax)"); in main()
42 asm volatile("setc 0x12345678(%rax)"); in main()
43 asm volatile("setnae 0x12345678(%rax)"); in main()
44 asm volatile("setae 0x12345678(%rax)"); in main()
[all …]
/linux/arch/arm/crypto/
H A Dchacha-scalar-core.S24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such
39 X12 .req r10
106 // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13)
107 _halfround X0, X4, X8_X10, X12, X1, X5, X9_X11, X13
110 __strd X8_X10, X9_X11, sp, 0
121 // quarterrounds: (x0, x5, x10, x15) and (x1, x6, x11, x12)
122 _halfround X0, X5, X8_X10, X15, X1, X6, X9_X11, X12
126 __ldrd X8_X10, X9_X11, sp, 0
133 .set brot, 0
134 .set drot, 0
[all …]
/linux/include/uapi/linux/
H A Dfs.h44 #define IO_INTEGRITY_CHK_GUARD (1U << 0) /* enforce guard check */
52 #define SEEK_SET 0 /* seek relative to beginning of file */
59 #define RENAME_NOREPLACE (1 << 0) /* Don't overwrite target */
95 #define FILE_DEDUPE_RANGE_SAME 0
105 * < 0 for error
154 #define FS_XFLAG_REALTIME 0x00000001 /* data in realtime volume */
155 #define FS_XFLAG_PREALLOC 0x00000002 /* preallocated file extents */
156 #define FS_XFLAG_IMMUTABLE 0x00000008 /* file cannot be modified */
157 #define FS_XFLAG_APPEND 0x00000010 /* all writes append */
158 #define FS_XFLAG_SYNC 0x0000002
[all...]
/linux/tools/perf/trace/beauty/include/uapi/linux/
H A Dfs.h43 #define SEEK_SET 0 /* seek relative to beginning of file */
50 #define RENAME_NOREPLACE (1 << 0) /* Don't overwrite target */
86 #define FILE_DEDUPE_RANGE_SAME 0
96 * < 0 for error
145 #define FS_XFLAG_REALTIME 0x00000001 /* data in realtime volume */
146 #define FS_XFLAG_PREALLOC 0x00000002 /* preallocated file extents */
147 #define FS_XFLAG_IMMUTABLE 0x00000008 /* file cannot be modified */
148 #define FS_XFLAG_APPEND 0x00000010 /* all writes append */
149 #define FS_XFLAG_SYNC 0x00000020 /* all writes synchronous */
150 #define FS_XFLAG_NOATIME 0x00000040 /* do not update access time */
[all …]
/linux/tools/include/uapi/linux/
H A Dfs.h43 #define SEEK_SET 0 /* seek relative to beginning of file */
50 #define RENAME_NOREPLACE (1 << 0) /* Don't overwrite target */
86 #define FILE_DEDUPE_RANGE_SAME 0
96 * < 0 for error
145 #define FS_XFLAG_REALTIME 0x00000001 /* data in realtime volume */
146 #define FS_XFLAG_PREALLOC 0x00000002 /* preallocated file extents */
147 #define FS_XFLAG_IMMUTABLE 0x00000008 /* file cannot be modified */
148 #define FS_XFLAG_APPEND 0x00000010 /* all writes append */
149 #define FS_XFLAG_SYNC 0x00000020 /* all writes synchronous */
150 #define FS_XFLAG_NOATIME 0x00000040 /* do not update access time */
[all …]
/linux/arch/arm64/crypto/
H A Dpoly1305-armv8.pl34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
78 mov $s1,#0xfffffffc0fffffff
79 movk $s1,#0x0fff,lsl#48
84 and $r0,$r0,$s1 // &=0ffffffc0fffffff
86 and $r1,$r1,$s1 // &=0ffffffc0ffffffc
145 cmp x17,#0 // is_base2_26?
233 cmp $r0,#0 // is_base2_26?
262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv770_smc.c34 #define FIRST_SMC_INT_VECT_REG 0xFFD8
35 #define FIRST_INT_VECT_S19 0xFFC0
38 0x08, 0x10, 0x08, 0x10,
39 0x08, 0x10, 0x08, 0x10,
40 0x08, 0x10, 0x08, 0x10,
41 0x08, 0x10, 0x08, 0x10,
42 0x08, 0x10, 0x08, 0x10,
43 0x08, 0x10, 0x08, 0x10,
44 0x08, 0x10, 0x08, 0x10,
45 0x08, 0x10, 0x08, 0x10,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/linux/drivers/memory/
H A Dmtk-smi.c24 #define SMI_L1LEN 0x100
26 #define SMI_L1_ARB 0x200
27 #define SMI_BUS_SEL 0x220
30 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
32 #define SMI_READ_FIFO_TH 0x230
33 #define SMI_M4U_TH 0x234
34 #define SMI_FIFO_TH1 0x238
35 #define SMI_FIFO_TH2 0x23c
36 #define SMI_DCM 0x300
37 #define SMI_DUMMY 0x444
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-jerry.dts25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
45 #size-cells = <0>;
52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_0_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_3_0_3_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-sitronix-st7703.c29 #define ST7703_CMD_ALL_PIXEL_OFF 0x22
30 #define ST7703_CMD_ALL_PIXEL_ON 0x23
31 #define ST7703_CMD_SETAPID 0xB1
32 #define ST7703_CMD_SETDISP 0xB2
33 #define ST7703_CMD_SETRGBIF 0xB3
34 #define ST7703_CMD_SETCYC 0xB4
35 #define ST7703_CMD_SETBGP 0xB5
36 #define ST7703_CMD_SETVCOM 0xB6
37 #define ST7703_CMD_SETOTP 0xB7
38 #define ST7703_CMD_SETPOWER_EXT 0xB8
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xF7",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xF7",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xF7",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xF7",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xF7",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xF7",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xF7",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xF7",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xF7",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xF7",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xF7",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xF7",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xF7",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xF7",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xF7",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
[all …]
/linux/arch/arm64/kernel/
H A Drelocate_kernel.S57 and x12, x16, PAGE_MASK /* x12 = addr */
58 sub x12, x12, x22 /* Convert x12 to virt */
65 copy_page x13, x12, x1, x2, x3, x4, x5, x6, x7, x8
71 mov x14, x12 /* ptr = addr */
75 mov x13, x12 /* dest = addr */
84 turn_off_mmu x12, x13
93 hvc #0 /* Jumps from el2 */
/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_phy.c18 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET BIT(0)
36 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT 0
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
45 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT 0
46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)
56 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT 0
57 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)
69 #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT 0
70 #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)
94 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT 0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]

12345678910>>...43