18 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET	BIT(0)
36 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT	0
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK	VC4_MASK(4, 0)
45 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT		0
46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK		VC4_MASK(4, 0)
56 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT	0
57 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK	VC4_MASK(3, 0)
69 #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT			0
70 #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK			VC4_MASK(5, 0)
94 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT		0
95 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK		VC4_MASK(3, 0)
103 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK	VC4_MASK(1, 0)
104 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT	0
106 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK		VC4_MASK(27, 0)
107 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT	0
109 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK		VC4_MASK(27, 0)
110 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT	0
114 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK	VC4_MASK(15, 0)
115 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT	0
122 #define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT			0
123 #define VC4_HDMI_RM_OFFSET_OFFSET_MASK			VC4_MASK(30, 0)
135 #define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP	BIT(0)
138 #define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK		VC4_MASK(9, 0)
141 #define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK		VC4_MASK(1, 0)
144 #define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_MASK	VC4_MASK(9, 0)
163 #define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN_MASK	VC4_MASK(0, 0)
166 #define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB	BIT(0)
168 #define VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP	BIT(0)
183 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_init()
184 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);  in vc4_hdmi_phy_init()
194 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_disable()
224 	unsigned int _vco_div = 0;  in phy_get_vco_freq()
225 	unsigned int _vco_sel = 0;  in phy_get_vco_freq()
244 		return 0x1c;  in phy_get_cp_current()
246 	return 0x18;  in phy_get_cp_current()
252 	u64 offset = 0;  in phy_get_rm_offset()
266 		return 0xf;  in phy_get_vco_gain()
269 		return 0xc;  in phy_get_vco_gain()
272 		return 0x6;  in phy_get_vco_gain()
275 		return 0x5;  in phy_get_vco_gain()
278 		return 0x7;  in phy_get_vco_gain()
280 	return 0x2;  in phy_get_vco_gain()
302 		0, 50000000,
304 			{{0x0, 0x0A}, 0x12, 0x0},
305 			{{0x0, 0x0A}, 0x12, 0x0},
306 			{{0x0, 0x0A}, 0x12, 0x0}
308 		{{0x0, 0x0A}, 0x18, 0x0},
313 			{{0x0, 0x09}, 0x12, 0x0},
314 			{{0x0, 0x09}, 0x12, 0x0},
315 			{{0x0, 0x09}, 0x12, 0x0}
317 		{{0x0, 0x0C}, 0x18, 0x3},
322 			{{0x0, 0x09}, 0x12, 0x0},
323 			{{0x0, 0x09}, 0x12, 0x0},
324 			{{0x0, 0x09}, 0x12, 0x0}
326 		{{0x0, 0x0C}, 0x18, 0x3},
331 			{{0x0, 0x0F}, 0x12, 0x1},
332 			{{0x0, 0x0F}, 0x12, 0x1},
333 			{{0x0, 0x0F}, 0x12, 0x1}
335 		{{0x0, 0x0C}, 0x18, 0x3},
340 			{{0x2, 0x0D}, 0x12, 0x1},
341 			{{0x2, 0x0D}, 0x12, 0x1},
342 			{{0x2, 0x0D}, 0x12, 0x1}
344 		{{0x0, 0x0C}, 0x18, 0xF},
349 			{{0x0, 0x1B}, 0x12, 0xF},
350 			{{0x0, 0x1B}, 0x12, 0xF},
351 			{{0x0, 0x1B}, 0x12, 0xF}
353 		{{0x0, 0x0A}, 0x12, 0xF},
358 			{{0x0, 0x1C}, 0x12, 0xF},
359 			{{0x0, 0x1C}, 0x12, 0xF},
360 			{{0x0, 0x1C}, 0x12, 0xF}
362 		{{0x0, 0x0B}, 0x13, 0xF},
371 	for (i = 0; i < count; i++) {  in phy_get_settings()
401 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x0f);  in vc5_hdmi_reset_phy()
441 		   VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));  in vc5_hdmi_phy_init()
446 		   VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));  in vc5_hdmi_phy_init()
457 		   VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |  in vc5_hdmi_phy_init()
458 		   VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));  in vc5_hdmi_phy_init()
471 		   VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP));  in vc5_hdmi_phy_init()
484 		word_sel = 0;  in vc5_hdmi_phy_init()
614 	div = 0;  in vc6_phy_get_vco_freq()
659 		0, 222000000,
918 	for (i = 0; i < count; i++) {  in vc6_phy_get_settings()
948 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);  in vc6_hdmi_reset_phy()
949 	HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);  in vc6_hdmi_reset_phy()
972 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_0, 0x810c6000);  in vc6_hdmi_phy_init()
973 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_1, 0x00b8c451);  in vc6_hdmi_phy_init()
974 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_2, 0x46402e31);  in vc6_hdmi_phy_init()
975 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_3, 0x00b8c005);  in vc6_hdmi_phy_init()
976 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_4, 0x42410261);  in vc6_hdmi_phy_init()
977 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_5, 0xcc021001);  in vc6_hdmi_phy_init()
978 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_6, 0xc8301c80);  in vc6_hdmi_phy_init()
979 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_7, 0xb0804444);  in vc6_hdmi_phy_init()
980 	HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_8, 0xf80f8000);  in vc6_hdmi_phy_init()
986 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x7f);  in vc6_hdmi_phy_init()
999 		   VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));  in vc6_hdmi_phy_init()
1172 		word_sel = 0;  in vc6_hdmi_phy_init()