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/linux/drivers/mfd/
H A Dwm8994-core.c32 .id = 0,
123 if (ret < 0) { in wm8994_suspend()
127 return 0; in wm8994_suspend()
154 if (ret != 0) in wm8994_suspend()
161 if (ret != 0) in wm8994_suspend()
169 if (ret != 0) { in wm8994_suspend()
174 return 0; in wm8994_suspend()
184 return 0; in wm8994_resume()
188 if (ret != 0) { in wm8994_resume()
195 if (ret != 0) { in wm8994_resume()
[all …]
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
44 return 0; in alloc_empty_config()
99 0), in test_stream()
158 return 0; in live_sanitycheck()
179 *cs++ = 0; in write_timestamp()
180 *cs++ = 0; in write_timestamp()
181 *cs++ = 0; in write_timestamp()
185 return 0; in write_timestamp()
221 for (i = 0; i < 4; i++) in live_noa_delay()
[all …]
/linux/drivers/of/unittest-data/
H A Doverlay_bad_add_dup_node.dtso18 power_bus = <0x1 0x2>;
25 power_bus_emergency = <0x101 0x102>;
/linux/include/soc/arc/
H A Dtimers.h12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
/linux/arch/powerpc/include/asm/
H A Dps3gpu.h16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
H A Dreg_fsl_emb.h38 #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
39 #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
40 #define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
41 #define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
42 #define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
43 #define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
44 #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
45 #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
46 #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
47 #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-data-modul-edm-sbc.dts28 reg = <0x0 0x40000000 0 0x40000000>;
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
69 gpio = <&gpio3 6 0>;
78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
[all …]
/linux/drivers/gpu/drm/xe/abi/
H A Dguc_errors_abi.h10 XE_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
11 XE_GUC_RESPONSE_ERROR_PROTOCOL = 0x04,
12 XE_GUC_RESPONSE_INVALID_STATE = 0x0A,
13 XE_GUC_RESPONSE_UNSUPPORTED_VERSION = 0x0B,
14 XE_GUC_RESPONSE_INVALID_VFID = 0x0C,
15 XE_GUC_RESPONSE_UNPROVISIONED_VF = 0x0D,
16 XE_GUC_RESPONSE_INVALID_EVENT = 0x0E,
17 XE_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
18 XE_GUC_RESPONSE_UNKNOWN_ACTION = 0x30,
19 XE_GUC_RESPONSE_ACTION_ABORTED = 0x31,
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dusb_a9g20-dab-mmx.dtsi21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
H A Dat91-kizboxmini-common.dtsi20 reg = <0x20000000 0x8000000>;
43 linux,code = <0x102>;
50 linux,code = <0x100>;
60 pwms = <&pwm0 2 10000000 0>;
68 pwms = <&pwm0 0 10000000 0>;
75 pwms = <&pwm0 1 10000000 0>;
95 pinctrl-0 = <&pinctrl_pwm0_pwm0_1
118 pinctrl-0 = <&pinctrl_ebi_addr_nand
126 pinctrl-0 = <&pinctrl_nand_oe_we
132 reg = <0x3 0x0 0x800000>;
[all …]
/linux/drivers/media/i2c/
H A Dwm8775.c40 #define ALC_HOLD 0x85 /* R17: use zero cross detection, ALC hold time 42.6 ms */
41 #define ALC_EN 0x100 /* R17: ALC enable */
50 u8 input; /* Last selected input (0-0xf) */
68 if (reg < 0 || reg >= TOT_REGS) { in wm8775_write()
73 for (i = 0; i < 3; i++) in wm8775_write()
75 (reg << 1) | (val >> 8), val & 0xff) == 0) in wm8775_write()
76 return 0; in wm8775_write()
85 int muted = 0 != state->mute->val; in wm8775_set_audio()
89 /* normalize ( 65535 to 0 -> 255 to 0 (+24dB to -103dB) ) */ in wm8775_set_audio()
95 wm8775_write(sd, R21, 0x0c0 | state->input); in wm8775_set_audio()
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/linux/arch/arm/mach-omap2/
H A Domap-secure.h16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
20 #define API_HAL_RET_VALUE_OK 0x00
21 #define API_HAL_RET_VALUE_FAIL 0x01
24 #define FLAG_START_CRITICAL 0x4
25 #define FLAG_IRQFIQ_MASK 0x3
26 #define FLAG_IRQ_ENABLE 0x2
27 #define FLAG_FIQ_ENABLE 0x1
28 #define NO_FLAG 0x0
33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
H A Domap-headsmp.S22 #define AUX_CORE_BOOT0_PA 0x48281800
23 #define API_HYP_ENTRY 0x102
46 mrc p15, 0, r4, c0, c0, 5
47 and r4, r4, #0x0f
64 mrc p15, 0, r4, c0, c0, 5
65 and r4, r4, #0x0f
70 smc #0
82 hold: ldr r12,=0x103
84 smc #0 @ read from AuxCoreBoot0
86 mrc p15, 0, r4, c0, c0, 5
[all …]
/linux/include/linux/mfd/
H A Didt82p33_reg.h10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h7 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
9 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
11 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
13 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
15 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
17 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
19 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
21 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
23 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
25 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json79 "EventCode": "0x34",
85 "EventCode": "0x35",
91 "EventCode": "0x102",
97 "EventCode": "0x103",
103 "EventCode": "0x104",
109 "EventCode": "0x105",
115 "EventCode": "0x106",
121 "EventCode": "0x107",
127 "EventCode": "0x111",
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-core.c45 #define CX25840_VID_INT_STAT_REG 0x410
46 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
47 #define CX25840_VID_INT_MASK_BITS 0xffff0000
49 #define CX25840_VID_INT_MASK_REG 0x412
51 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
52 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
53 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
56 #define CX25840_AUD_INT_CTRL_REG 0x812
57 #define CX25840_AUD_INT_STAT_REG 0x813
59 #define CX23885_PIN_CTRL_IRQ_REG 0x123
[all …]
/linux/drivers/usb/renesas_usbhs/
H A Drcar3.c13 #define LPSTS 0x102
14 #define UGCTRL 0x180 /* 32-bit register */
15 #define UGCTRL2 0x184 /* 32-bit register */
16 #define UGSTS 0x188 /* 32-bit register */
19 #define LPSTS_SUSPM 0x4000
22 #define UGCTRL_PLLRESET 0x00000001
23 #define UGCTRL_CONNECT 0x00000004
27 * Remarks: bit[31:11] and bit[9:6] should be 0
29 #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
30 #define UGCTRL2_USB0SEL_HSUSB 0x00000020
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio_marduk.dts31 reg = <0x00000000 0x10000000>;
64 linux,code = <0x101>; /* BTN_1 */
69 linux,code = <0x102>; /* BTN_2 */
82 pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
85 cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
87 flash@0 {
89 reg = <0>;
136 pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
144 adc-reserved-channels = <0x10>;
153 reg = <0x20>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6755.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0x000>;
36 reg = <0x001>;
43 reg = <0x002>;
50 reg = <0x003>;
57 reg = <0x100>;
64 reg = <0x101>;
71 reg = <0x102>;
78 reg = <0x103>;
[all …]
/linux/include/uapi/sound/
H A Dskl-tplg-interface.h16 * Default types range from 0~12. type can range from 0 to 0xff
19 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100
20 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
21 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103
22 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104
30 /* Reserve event type 0 for no event handlers */
32 SKL_EVENT_NONE = 0,
57 SKL_CH_CFG_MONO = 0,
75 SKL_MODULE_TYPE_MIXER = 0,
86 SKL_AFFINITY_CORE_0 = 0,
[all …]
H A Dtlv.h6 #define SNDRV_CTL_TLVT_CONTAINER 0 /* one level down - group of TLVs */
17 #define SNDRV_CTL_TLVT_CHMAP_FIXED 0x101 /* fixed channel position */
18 #define SNDRV_CTL_TLVT_CHMAP_VAR 0x102 /* channels freely swappable */
19 #define SNDRV_CTL_TLVT_CHMAP_PAIRED 0x103 /* pair-wise swappable */
35 #define SNDRV_CTL_TLVO_TYPE 0
45 #define SNDRV_CTL_TLVD_DB_SCALE_MASK 0xffff
46 #define SNDRV_CTL_TLVD_DB_SCALE_MUTE 0x10000
51 ((mute) ? SNDRV_CTL_TLVD_DB_SCALE_MUTE : 0))
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b.dtsi13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
59 reg = <0x0 0x1>;
69 reg = <0x0 0x100>;
79 reg = <0x0 0x101>;
89 reg = <0x0 0x102>;
99 reg = <0x0 0x103>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]

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