Lines Matching +full:0 +full:x102
8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
27 <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */
28 <0x104 &gic_its 0x2200 0x1>, /* PF4 */
29 <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */
30 <0x105 &gic_its 0x2280 0x1>, /* PF5 */
31 <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */
32 <0x106 &gic_its 0x2300 0x1>, /* PF6 */
33 <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */
34 <0x107 &gic_its 0x2380 0x1>, /* PF7 */
35 <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */
45 ranges = <0x0 0x0 0x40000000 0x800>;
47 pcie_phy: phy@0 {
49 reg = <0x0 0x200>;