Lines Matching +full:0 +full:x102

7 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT                          0x100
9 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT                          0x101
11 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT                          0x102
13 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT                          0x103
15 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT                          0x104
17 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT                          0x105
19 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT                         0x106
21 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT                         0x107
23 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT                       0x108
25 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT                       0x109
27 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR                        0x10A
30 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT			0x10B
32 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT			0x10C
34 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT			0x10D
36 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT			0x10E
38 #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT                       0x10F
40 #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT                       0x110
42 #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT                       0x111
44 #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT                       0x112
46 #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT                       0x113
48 #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT                       0x114
50 #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT                       0x115
53 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR                         0x116
55 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK			0x305
56 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK			0x306
58 #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK				0x307
59 #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK			0x308
61 #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK				0x30c
62 #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK			0x30d
64 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK				0x30e
65 #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK			0x30f
68 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310
70 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311
72 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312
74 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313
76 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314
78 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315
80 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316
82 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317
84 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
87 #define Q6PRM_LPASS_CLK_ROOT_DEFAULT	0