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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8112-j493.dts27 led-0 {
28 pwms = <&fpwm1 0 40000>;
45 wifi0: wifi@0,0 {
47 reg = <0x10000 0x0 0x0 0x0 0x0>;
54 bluetooth0: bluetooth@0,1 {
56 reg = <0x10100 0x0 0x0 0x0 0x0>;
H A Dt8112-j413.dts27 led-0 {
28 pwms = <&fpwm1 0 40000>;
45 wifi0: wifi@0,0 {
47 reg = <0x10000 0x0 0x0 0x0 0x0>;
54 bluetooth0: bluetooth@0,1 {
56 reg = <0x10100 0x0 0x0 0x0 0x0>;
67 reg = <0x3a>;
H A Dt8103-jxxx.dtsi27 framebuffer0: framebuffer@0 {
29 reg = <0 0 0 0>; /* To be filled by loader */
37 reg = <0x8 0 0x2 0>; /* To be filled by loader */
52 reg = <0x38>;
60 reg = <0x3f>;
74 wifi0: network@0,0 {
76 reg = <0x10000 0x0 0x0 0x0 0x0>;
82 bluetooth0: bluetooth@0,1 {
84 reg = <0x10100 0x0 0x0 0x0 0x0>;
H A Dt600x-common.dtsi16 #size-cells = <0>;
59 cpu_e00: cpu@0 {
62 reg = <0x0 0x0>;
64 cpu-release-addr = <0 0>; /* To be filled by loader */
66 i-cache-size = <0x20000>;
67 d-cache-size = <0x10000>;
76 reg = <0x0 0x1>;
78 cpu-release-addr = <0 0>; /* To be filled by loader */
80 i-cache-size = <0x20000>;
81 d-cache-size = <0x10000>;
[all …]
H A Dt8103.dtsi23 #size-cells = <0>;
57 cpu_e0: cpu@0 {
60 reg = <0x0 0x0>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
74 reg = <0x0 0x1>;
76 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
[all …]
H A Dt8112.dtsi24 #size-cells = <0>;
58 cpu_e0: cpu@0 {
61 reg = <0x0 0x0>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
75 reg = <0x0 0x1>;
77 cpu-release-addr = <0 0>; /* To be filled by loader */
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
[all …]
/freebsd/sys/dts/
H A Dbindings-gpio.txt41 reg = <0x10100 0x20>;
67 gpios = <&GPIO 0 1 /* GPIO[0]: FLAGS */
76 pin: 0-MAX GPIO pin number.
83 GPIO_PIN_INPUT 0x0001 Input direction
84 GPIO_PIN_OUTPUT 0x0002 Output direction
85 GPIO_PIN_OPENDRAIN 0x0004 Open-drain output
86 GPIO_PIN_OPENSOURCE 0x0008 Open-source output
87 GPIO_PIN_PUSHPULL 0x0010 Push-pull output
88 GPIO_PIN_TRISTATE 0x0020 Output disabled
89 GPIO_PIN_PULLUP 0x0040 Internal pull-up enabled
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml35 const: 0
51 #size-cells = <0>;
53 cpu@0 {
56 reg = <0x0 0x0>;
64 reg = <0x0 0x10100>;
70 ecluster_opp: opp-table-0 {
108 reg = <0x2 0x10e20000 0 0x1000>;
109 #performance-domain-cells = <0>;
114 reg = <0x2 0x11e20000 0 0x1000>;
115 #performance-domain-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
H A Didle-states.yaml82 between 0 and infinite time, until a wake-up event occurs.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
147 0| 1 time(ms)
152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
332 #size-cells = <0>;
335 cpu@0 {
338 reg = <0x0 0x0>;
347 reg = <0x0 0x1>;
356 reg = <0x0 0x100>;
365 reg = <0x0 0x101>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dorion5x.dtsi24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov920.dtsi38 #clock-cells = <0>;
44 #size-cells = <0>;
87 cpu0: cpu@0 {
90 reg = <0x0 0x0>;
97 reg = <0x0 0x100>;
104 reg = <0x0 0x200>;
111 reg = <0x0 0x300>;
118 reg = <0x0 0x10000>;
125 reg = <0x0 0x10100>;
132 reg = <0x0 0x10200>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
[all...]
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x000>;
52 i-cache-size = <0x8000>;
55 d-cache-size = <0x8000>;
63 reg = <0x0 0x100>;
65 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
76 reg = <0x0 0x200>;
[all …]
/freebsd/sys/dev/safexcel/
H A Dsafexcel_reg.h30 #define SAFEXCEL_HIA_VERSION_LE 0x35ca
31 #define SAFEXCEL_HIA_VERSION_BE 0xca35
32 #define EIP201_VERSION_LE 0x36c9
33 #define SAFEXCEL_REG_LO16(_reg) ((_reg) & 0xffff)
34 #define SAFEXCEL_REG_HI16(_reg) (((_reg) >> 16) & 0xffff)
37 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
38 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
39 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
40 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
41 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_chan.c69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | in r12a_write_txpower_ht()
99 /* 1SS, MCS 0..3 */ in r12a_write_txpower_vht()
101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) | in r12a_write_txpower_vht()
102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) | in r12a_write_txpower_vht()
103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) | in r12a_write_txpower_vht()
104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)])); in r12a_write_txpower_vht()
108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) | in r12a_write_txpower_vht()
109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) | in r12a_write_txpower_vht()
110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) | in r12a_write_txpower_vht()
111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)])); in r12a_write_txpower_vht()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVSymbolicOperands.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
123 def : ExtensionEntry<category, value, reqExtensions[0]>;
193 defm : SymbolicOperandWithRequirements<ExtensionOperand, value, NAME, 0, 0, [], []>;
330 defm Matrix : CapabilityOperand<0, 0, 0, [], []>;
331 defm Shader : CapabilityOperand<1, 0, 0, [], [Matrix]>;
332 defm Geometry : CapabilityOperand<2, 0, 0, [], [Shader]>;
333 defm Tessellation : CapabilityOperand<3, 0, 0, [], [Shader]>;
334 defm Addresses : CapabilityOperand<4, 0, 0, [], []>;
335 defm Linkage : CapabilityOperand<5, 0, 0, [], []>;
336 defm Kernel : CapabilityOperand<6, 0, 0, [], []>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]

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