Searched +full:0 +full:x10080000 (Results 1 – 6 of 6) sorted by relevance
32 #clock-cells = <0>;38 #clock-cells = <0>;44 #clock-cells = <0>;51 reg = <0x20 0x10020000 0 0x20000>;58 #address-cells = <0>;60 reg = <0x20 0x01001000 0 0x1000>,61 <0x20 0x01002000 0 0x2000>,62 <0x20 0x01004000 0 0x2000>,63 <0x20 0x01006000 0 0x2000>;97 reg = <0x20 0x10030000 0 0x2000>;[all …]
23 #size-cells = <0>;26 cpu0: cpu@0 {30 reg = <0x0>;47 reg = <0x1>;74 reg = <0x10080000 0x10000>;77 ranges = <0 0x10080000 0x10000>;79 smp-sram@0 {81 reg = <0x0 0x50>;87 reg = <0x1010c000 0x19c>;102 #size-cells = <0>;[all …]
18 #size-cells = <0>;21 cpu0: cpu@0 {25 reg = <0x0>;34 reg = <0x1>;42 reg = <0x2>;50 reg = <0x3>;56 cpu0_opp_table: opp-table-0 {103 reg = <0x10080000 0x8000>;106 ranges = <0 0x10080000 0x8000>;108 smp-sram@0 {[all …]
29 #size-cells = <0>;34 reg = <0xf00>;42 cpu_opp_table: opp-table-0 {84 #clock-cells = <0>;89 reg = <0x10080000 0x2000>;92 ranges = <0 0x10080000 0x2000>;97 reg = <0x10210000 0x100>;106 pinctrl-0 = <&uart2m0_xfer>;112 reg = <0x10220000 0x100>;121 pinctrl-0 = <&uart1_xfer>;[all …]
44 #size-cells = <0>;50 reg = <0xf00>;60 reg = <0xf01>;68 reg = <0xf02>;76 reg = <0xf03>;82 cpu_opp_table: opp-table-0 {165 #clock-cells = <0>;170 reg = <0x10080000 0x2000>;173 ranges = <0 0x10080000 0x2000>;175 smp-sram@0 {[all …]
20 #size-cells = <0>;22 S7_0: cpu@0 {24 reg = <0>;205 cpu_opp: opp-table-0 {265 #clock-cells = <0>;270 #clock-cells = <0>;276 #clock-cells = <0>;283 #clock-cells = <0>;290 #clock-cells = <0>;296 #clock-cells = <0>;[all …]