Home
last modified time | relevance | path

Searched +full:0 +full:x10080000 (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dlsi,axm5516-clks.txt18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4357.dtsi18 cpu@0 {
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
/linux/arch/m68k/coldfire/
H A Dm53xx.c31 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
32 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
33 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
34 DEFINE_CLK(0, "edma", 17, MCF_CLK);
35 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
36 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
37 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
39 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
40 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
30 reg = <0x0>;
47 reg = <0x1>;
74 reg = <0x10080000 0x10000>;
77 ranges = <0 0x10080000 0x10000>;
79 smp-sram@0 {
81 reg = <0x0 0x50>;
87 reg = <0x1010c000 0x19c>;
102 #size-cells = <0>;
[all …]
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
35 reg = <0x1>;
43 reg = <0x2>;
51 reg = <0x3>;
57 cpu0_opp_table: opp-table-0 {
104 reg = <0x10080000 0x8000>;
107 ranges = <0 0x10080000 0x8000>;
109 smp-sram@0 {
[all …]
H A Drk3036.dtsi37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
[all …]
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
[all …]
H A Drk3128.dtsi44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
159 #clock-cells = <0>;
164 reg = <0x10080000 0x2000>;
167 ranges = <0 0x10080000 0x2000>;
169 smp-sram@0 {
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg.h49 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
54 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
61 #define MSR_LE_LG 0 /* Little Endian */
75 #define MSR_SF 0
76 #define MSR_HV 0
77 #define MSR_S 0
85 #define MSR_SPE 0
99 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
104 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
116 #define MSR_TS_N 0 /* Non-transactional */
[all …]