Lines Matching +full:0 +full:x10080000
23 #size-cells = <0>;
26 cpu0: cpu@0 {
30 reg = <0x0>;
47 reg = <0x1>;
74 reg = <0x10080000 0x10000>;
77 ranges = <0 0x10080000 0x10000>;
79 smp-sram@0 {
81 reg = <0x0 0x50>;
87 reg = <0x1010c000 0x19c>;
102 #size-cells = <0>;
104 vop0_out_hdmi: endpoint@0 {
105 reg = <0>;
113 reg = <0x1010e000 0x19c>;
128 #size-cells = <0>;
130 vop1_out_hdmi: endpoint@0 {
131 reg = <0>;
139 reg = <0x10116000 0x2000>;
144 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
147 #sound-dai-cells = <0>;
152 #size-cells = <0>;
154 hdmi_in: port@0 {
155 reg = <0>;
157 #size-cells = <0>;
159 hdmi_in_vop0: endpoint@0 {
160 reg = <0>;
178 reg = <0x10118000 0x2000>;
181 pinctrl-0 = <&i2s0_bus>;
188 #sound-dai-cells = <0>;
194 reg = <0x1011a000 0x2000>;
197 pinctrl-0 = <&i2s1_bus>;
204 #sound-dai-cells = <0>;
210 reg = <0x1011c000 0x2000>;
213 pinctrl-0 = <&i2s2_bus>;
220 #sound-dai-cells = <0>;
226 reg = <0x20000000 0x1000>;
244 reg = <0x2000e000 0x100>;
252 reg = <0x20010000 0x4000>;
259 reg = <0x17 0x1>;
265 reg = <0x20038000 0x100>;
273 reg = <0x2003a000 0x100>;
281 reg = <0x20060000 0x100>;
300 reg = <0x20034000 0x100>;
313 reg = <0x2003c000 0x100>;
326 reg = <0x2003e000 0x100>;
339 reg = <0x20080000 0x100>;
352 reg = <0x20084000 0x100>;
365 reg = <0x2000a000 0x100>;
425 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
429 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
430 <0 RK_PA2 1 &pcfg_pull_none>;
471 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
477 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
483 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
489 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
642 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
643 <0 RK_PB0 1 &pcfg_pull_default>,
644 <0 RK_PB1 1 &pcfg_pull_default>,
645 <0 RK_PB2 1 &pcfg_pull_default>,
646 <0 RK_PB3 1 &pcfg_pull_default>,
647 <0 RK_PB4 1 &pcfg_pull_default>,
648 <0 RK_PB5 1 &pcfg_pull_default>,
649 <0 RK_PB6 1 &pcfg_pull_default>,
650 <0 RK_PB7 1 &pcfg_pull_default>;
656 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
657 <0 RK_PC1 1 &pcfg_pull_default>,
658 <0 RK_PC2 1 &pcfg_pull_default>,
659 <0 RK_PC3 1 &pcfg_pull_default>,
660 <0 RK_PC4 1 &pcfg_pull_default>,
661 <0 RK_PC5 1 &pcfg_pull_default>;
667 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
668 <0 RK_PD1 1 &pcfg_pull_default>,
669 <0 RK_PD2 1 &pcfg_pull_default>,
670 <0 RK_PD3 1 &pcfg_pull_default>,
671 <0 RK_PD4 1 &pcfg_pull_default>,
672 <0 RK_PD5 1 &pcfg_pull_default>;
709 #size-cells = <0>;
713 reg = <0x17c>;
716 #clock-cells = <0>;
717 #phy-cells = <0>;
721 reg = <0x188>;
724 #clock-cells = <0>;
725 #phy-cells = <0>;
732 pinctrl-0 = <&i2c0_xfer>;
737 pinctrl-0 = <&i2c1_xfer>;
742 pinctrl-0 = <&i2c2_xfer>;
747 pinctrl-0 = <&i2c3_xfer>;
752 pinctrl-0 = <&i2c4_xfer>;
761 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
768 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
781 #size-cells = <0>;
808 #power-domain-cells = <0>;
818 #power-domain-cells = <0>;
825 #power-domain-cells = <0>;
832 pinctrl-0 = <&pwm0_out>;
837 pinctrl-0 = <&pwm1_out>;
842 pinctrl-0 = <&pwm2_out>;
847 pinctrl-0 = <&pwm3_out>;
852 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
857 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
862 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
865 pinctrl-0 = <&uart0_xfer>;
873 pinctrl-0 = <&uart1_xfer>;
881 pinctrl-0 = <&uart2_xfer>;
889 pinctrl-0 = <&uart3_xfer>;