Lines Matching +full:0 +full:x10080000
37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
136 reg = <0x10108800 0x100>;
141 #iommu-cells = <0>;
146 reg = <0x10118000 0x19c>;
158 #size-cells = <0>;
159 vop_out_hdmi: endpoint@0 {
160 reg = <0>;
168 reg = <0x10118300 0x100>;
173 #iommu-cells = <0>;
179 reg = <0x1012d000 0x20>;
184 reg = <0x1012e000 0x20>;
189 reg = <0x1012f000 0x20>;
196 #address-cells = <0>;
198 reg = <0x10139000 0x1000>,
199 <0x1013a000 0x2000>,
200 <0x1013c000 0x2000>,
201 <0x1013e000 0x2000>;
208 reg = <0x10180000 0x40000>;
222 reg = <0x101c0000 0x40000>;
232 reg = <0x10200000 0x4000>;
251 reg = <0x10214000 0x4000>;
256 fifo-depth = <0x100>;
265 reg = <0x10218000 0x4000>;
270 fifo-depth = <0x100>;
279 reg = <0x1021c000 0x4000>;
291 fifo-depth = <0x100>;
295 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
303 reg = <0x10220000 0x4000>;
307 dmas = <&pdma 0>, <&pdma 1>;
310 pinctrl-0 = <&i2s_bus>;
311 #sound-dai-cells = <0>;
318 reg = <0x10500000 0x4000>;
324 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
332 reg = <0x20000000 0x1000>;
344 reg = <0x20008000 0x1000>;
350 #size-cells = <0>;
358 #power-domain-cells = <0>;
366 #power-domain-cells = <0>;
373 #power-domain-cells = <0>;
379 offset = <0x1d8>;
389 reg = <0x20030000 0x4000>;
393 #sound-dai-cells = <0>;
399 reg = <0x20034000 0x4000>;
404 pinctrl-0 = <&hdmi_ctl>;
405 #sound-dai-cells = <0>;
410 #size-cells = <0>;
412 hdmi_in: port@0 {
413 reg = <0>;
428 reg = <0x20044000 0x20>;
436 reg = <0x20050000 0x10>;
440 pinctrl-0 = <&pwm0_pin>;
446 reg = <0x20050010 0x10>;
450 pinctrl-0 = <&pwm1_pin>;
456 reg = <0x20050020 0x10>;
460 pinctrl-0 = <&pwm2_pin>;
466 reg = <0x20050030 0x10>;
470 pinctrl-0 = <&pwm3_pin>;
476 reg = <0x20056000 0x1000>;
479 #size-cells = <0>;
483 pinctrl-0 = <&i2c1_xfer>;
489 reg = <0x2005a000 0x1000>;
492 #size-cells = <0>;
496 pinctrl-0 = <&i2c2_xfer>;
502 reg = <0x20060000 0x100>;
510 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
516 reg = <0x20064000 0x100>;
524 pinctrl-0 = <&uart1_xfer>;
530 reg = <0x20068000 0x100>;
538 pinctrl-0 = <&uart2_xfer>;
544 reg = <0x20072000 0x1000>;
547 #size-cells = <0>;
551 pinctrl-0 = <&i2c0_xfer>;
557 reg = <0x20074000 0x1000>;
564 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
566 #size-cells = <0>;
572 reg = <0x20078000 0x4000>;
573 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
591 reg = <0x2007c000 0x100>;
604 reg = <0x20080000 0x100>;
617 reg = <0x20084000 0x100>;
638 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
644 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
650 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
656 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
687 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
691 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
692 <0 RK_PB4 1 &pcfg_pull_default>,
693 <0 RK_PB5 1 &pcfg_pull_default>,
694 <0 RK_PB6 1 &pcfg_pull_default>;
698 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
702 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
788 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
789 <0 RK_PA1 1 &pcfg_pull_none>;
795 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
796 <0 RK_PA3 1 &pcfg_pull_none>;
829 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
830 <0 RK_PC1 1 &pcfg_pull_none>;
834 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
838 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;