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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml35 pattern: "^switch@[0-9a-f]+$"
103 const: 0
106 "^port@[0-9a-f]+$":
131 minimum: 0
138 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
140 enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
141 default: 0
147 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
149 enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
150 default: 0
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen9_renderstate.c11 0x000007a8,
12 0x000007b4,
13 0x000007bc,
14 0x000007cc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
H A Dgen8_renderstate.c11 0x00000798,
12 0x000007a4,
13 0x000007ac,
14 0x000007bc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/linux/drivers/comedi/drivers/
H A Ds626.h36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
39 #define S626_EOPL 0x80 /* End of ADC poll list marker. */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
44 #define S626_ERR_ILLEGAL_PARM 0x00010000 /*
48 #define S626_ERR_I2C 0x00020000 /* I2C error. */
49 #define S626_ERR_COUNTERSETUP 0x00200000 /*
53 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
74 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c56 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
163 u32 bw_index = 0; in a6xx_gmu_set_freq()
165 int ret = 0; in a6xx_gmu_set_freq()
172 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) in a6xx_gmu_set_freq()
178 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); in a6xx_gmu_set_freq()
180 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { in a6xx_gmu_set_freq()
229 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); in a6xx_gmu_set_freq()
232 ((3 & 0xf) << 28) | perf_index); in a6xx_gmu_set_freq()
238 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); in a6xx_gmu_set_freq()
298 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); in a6xx_gmu_start()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dglymur.dtsi41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
49 power-domains = <&cpu_pd0>, <&scmi_perf 0>;
64 reg = <0x0 0x100>;
67 power-domains = <&cpu_pd1>, <&scmi_perf 0>;
76 reg = <0x0 0x200>;
79 power-domains = <&cpu_pd2>, <&scmi_perf 0>;
88 reg = <0x0 0x300>;
91 power-domains = <&cpu_pd3>, <&scmi_perf 0>;
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