Lines Matching +full:0 +full:x10004000
55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
117 u32 bw_index = 0;
119 int ret = 0;
126 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
132 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0);
134 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) {
183 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
186 ((3 & 0xf) << 28) | perf_index);
192 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
247 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
248 if (val <= 0x20010004) {
249 mask = 0xffffffff;
250 reset_val = 0xbabeface;
252 mask = 0x1ff;
253 reset_val = 0x100;
262 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0);
264 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
267 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
372 "Timeout waiting for GMU OOB set %s: 0x%x\n",
407 return 0;
409 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
412 (val & 0x38) == 0x28, 1, 100);
415 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
419 return 0;
432 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
434 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
437 (val & 0x04), 100, 10000);
440 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
450 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
455 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
456 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
473 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));
482 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
502 != 0x0f) {
512 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
538 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
540 return 0;
555 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
584 pdc_address_offset = 0x30090;
586 pdc_address_offset = 0x300a0;
588 pdc_address_offset = 0x30080;
601 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
602 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
603 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
604 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
606 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000);
607 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
608 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
609 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
610 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
611 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
620 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0);
621 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab);
622 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581);
623 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2);
624 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad);
626 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
627 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
628 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
629 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
630 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
637 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
638 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
639 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
640 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
641 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
645 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
646 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
647 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
648 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
650 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
651 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
652 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
654 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
656 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
659 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
660 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
661 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
662 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
665 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
666 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
669 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
671 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
672 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
674 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
678 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
679 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
695 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
696 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
699 #define GMU_PWR_COL_HYST 0x000a1680
708 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
709 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
710 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
716 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
722 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
729 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
735 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
770 u32 itcm_base = 0x00000000;
771 u32 dtcm_base = 0x00040000;
774 dtcm_base = 0x10004000;
778 if (fw_image->size > 0x8000) {
786 return 0;
793 if (blk->size == 0)
810 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
811 blk->addr, blk->size, blk->data[0]);
821 return 0;
830 u32 chipid = 0;
864 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
865 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
872 fence_range_upper = 0x32;
873 fence_range_lower = 0x8a0;
875 fence_range_upper = 0xa;
876 fence_range_lower = 0xa0;
882 FIELD_PREP(GENMASK(17, 0), fence_range_lower));
888 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
900 chipid = adreno_gpu->chip_id & 0xffff0000;
901 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
902 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
909 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));
944 return 0;
960 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
961 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
968 u32 val, seqmem_off = 0;
996 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1013 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
1014 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1037 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
1093 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
1124 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
1203 "Unable to slumber GMU: status = 0%x/0%x\n",
1231 return 0;
1257 return 0;
1287 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1288 range_end = 0x80000000;
1313 return 0;
1320 mmu = msm_iommu_new(gmu->dev, 0);
1326 gmu->vm = msm_gem_vm_create(drm, mmu, "gmu", 0x0, 0x80000000, true);
1330 return 0;
1351 const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 };
1352 unsigned int bcm_index, bw_index, bcm_count = 0;
1355 for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) {
1377 for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) {
1382 for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) {
1394 data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0);
1399 u32 perfmode = 0;
1406 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode);
1424 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote);
1428 return 0;
1439 return 0;
1443 return 0;
1485 for (i = 0; i < freqs_count; i++) {
1486 u8 pindex = 0, sindex = 0;
1490 for (j = 0; j < pri_count; j++) {
1502 for (j = 0; j < pri_count; j++)
1513 for (j = 0; j < sec_count; j++) {
1523 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1527 return 0;
1566 int i, index = 0;
1579 freqs[index++] = 0;
1581 for (i = 0; i < count; i++) {
1598 int i, index = 0;
1611 bandwidths[index++] = 0;
1613 for (i = 0; i < count; i++) {
1614 opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0);
1632 int ret = 0;
1674 int ret, i, cmd_idx = 0;
1680 return 0;
1685 cmd->enable_by_level = 0;
1687 /* Skip freq = 0 and parse acd-level for rest of the OPPs */
1722 return 0;
1734 return 0;
1752 return 0;
1850 return 0;
1904 return 0;
1960 0x60400000, "debug");
1969 0x60000000, "dummy");
1977 SZ_16M - SZ_16K, 0x04000, "icache");
1988 SZ_256K - SZ_16K, 0x04000, "icache");
1993 SZ_256K - SZ_16K, 0x44000, "dcache");
2001 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");
2007 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");
2012 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
2031 gmu->rscc = gmu->mmio + 0x23000;
2038 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
2087 return 0;