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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dingenic,intc.yaml14 pattern: "^interrupt-controller@[0-9a-f]+$"
59 reg = <0x10001000 0x40>;
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,imx-dma.yaml64 reg = <0x10001000 0x1000>;
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8192-sys-clock.yaml45 reg = <0x10000000 0x1000>;
52 reg = <0x10001000 0x1000>;
59 reg = <0x10003000 0x1000>;
66 reg = <0x1000c000 0x1000>;
H A Dmediatek,mt8195-sys-clock.yaml53 reg = <0x10000000 0x1000>;
60 reg = <0x10001000 0x1000>;
67 reg = <0x1000c000 0x1000>;
74 reg = <0x11003000 0x1000>;
H A Dmediatek,infracfg.yaml84 reg = <0x10001000 0x1000>;
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x67800000 0x00 0x00080000>,
12 <0x00 0x67e00000 0x00 0x0000c000>;
18 ti,sci-proc-ids = <0x33 0xff>;
24 reg = <0x00 0x02920000 0x00 0x1000>,
25 <0x00 0x02927000 0x00 0x400>,
26 <0x00 0x0e000000 0x00 0x00800000>,
27 <0x44 0x00000000 0x00 0x00001000>;
28 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
29 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
37 clocks = <&k3_clks 334 0>;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x0 0x0>;
28 reg = <0x0 0x1>;
35 reg = <0x0 0x2>;
42 reg = <0x0 0x3>;
49 reg = <0 0x10003000 0 0x1000>;
63 reg = <0 0x10001000 0 0x1000>;
77 #size-cells = <0>;
79 port@0 {
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
H A Dbcm6328.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
55 #address-cells = <0>;
71 reg = <0x10000004 0x4>;
77 reg = <0x10000010 0x4>;
83 reg = <0x10000020 0x10>,
84 <0x10000030 0x10>;
[all …]
H A Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/linux/lib/crypto/
H A Ddes.c30 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
31 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
32 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
33 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
34 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
35 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
36 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
37 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
38 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
39 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_reg.h25 #define MHCCIF_RC_DEV_BASE 0x10024000
27 #define REG_RC2EP_SW_BSY 0x04
28 #define REG_RC2EP_SW_INT_START 0x08
30 #define REG_RC2EP_SW_TCHNUM 0x0c
42 #define REG_EP2RC_SW_INT_STS 0x10
43 #define REG_EP2RC_SW_INT_ACK 0x14
44 #define REG_EP2RC_SW_INT_EAP_MASK 0x20
45 #define REG_EP2RC_SW_INT_EAP_MASK_SET 0x30
46 #define REG_EP2RC_SW_INT_EAP_MASK_CLR 0x40
48 #define D2H_INT_DS_LOCK_ACK BIT(0)
[all …]
/linux/arch/powerpc/boot/dts/
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
/linux/drivers/net/ethernet/packetengines/
H A Dyellowfin.c35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
117 module_param(max_interrupt_work, int, 0);
118 module_param(mtu, int, 0);
119 module_param(debug, int, 0);
[all …]

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