35 static int debug = 1;			/* 1 normal messages, 0 quiet .. 7 verbose. */
42 static int dma_ctrl = 0x004A0263; 			/* Constrained by errata */
43 static int fifo_cfg = 0x0020;				/* Bypass external Tx FIFO. */
45 static int dma_ctrl = 0x00CAC277;			/* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; 			/* Constrained by errata */
49 static const int fifo_cfg = 0x0020;				/* Bypass external Tx FIFO. */
117 module_param(max_interrupt_work, int, 0);
118 module_param(mtu, int, 0);
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(options, int, NULL, 0);
122 module_param_array(full_duplex, int, NULL, 0);
123 module_param(gx_fix, int, 0);
126 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
200    Data Manual v3.0
219 	YELLOWFIN_SIZE	= 0x100,
232 	{"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
234 	{"Symbios SYM83C885", { 0x07011000, 0xffffffff},
240 	{ 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 	{ 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
249 	TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 	TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 	RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 	RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 	EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 	ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 	Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 	MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
257 	MII_Status=0xAE,
258 	RxDepth=0xB8, FlowCtrl=0xBC,
259 	AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 	EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
261 	EEFeature=0xF5,
289 	CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 	CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 	BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 	BRANCH_IFTRUE=0x040000,
296 enum desc_status_bits { RX_EOP=0x0040, };
300 	IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 	IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 	IntrEarlyRx=0x100, IntrWakeup=0x200, };
378 	int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;  in yellowfin_init_one()
383 	int bar = 0;  in yellowfin_init_one()
419 		for (i = 0; i < 6; i++)  in yellowfin_init_one()
422 		int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);  in yellowfin_init_one()
423 		for (i = 0; i < 6; i++)  in yellowfin_init_one()
429 	iowrite32(0x80000000, ioaddr + DMACtrl);  in yellowfin_init_one()
464 	if (option > 0) {  in yellowfin_init_one()
465 		if (option & 0x200)  in yellowfin_init_one()
471 	if (find_cnt < MAX_UNITS  &&  full_duplex[find_cnt] > 0)  in yellowfin_init_one()
495 		int phy, phy_idx = 0;  in yellowfin_init_one()
496 		for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {  in yellowfin_init_one()
498 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {  in yellowfin_init_one()
501 				netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",  in yellowfin_init_one()
510 	return 0;  in yellowfin_init_one()
535 	iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);  in read_eeprom()
536 	while ((ioread8(ioaddr + EEStatus) & 0x80)  &&  --bogus_cnt > 0)  in read_eeprom()
551 	for (i = 10000; i >= 0; i--)  in mdio_read()
552 		if ((ioread16(ioaddr + MII_Status) & 1) == 0)  in mdio_read()
565 	for (i = 10000; i >= 0; i--)  in mdio_write()
566 		if ((ioread16(ioaddr + MII_Status) & 1) == 0)  in mdio_write()
579 	iowrite32(0x80000000, ioaddr + DMACtrl);  in yellowfin_open()
586 	if (rc < 0)  in yellowfin_open()
592 	for (i = 0; i < 6; i++)  in yellowfin_open()
597 	iowrite32(0x00800080, ioaddr + TxIntrSel); 	/* Interrupt on Tx abort */  in yellowfin_open()
598 	iowrite32(0x00800080, ioaddr + TxBranchSel);	/* Branch on Tx abort */  in yellowfin_open()
599 	iowrite32(0x00400040, ioaddr + TxWaitSel); 	/* Wait on Tx status */  in yellowfin_open()
600 	iowrite32(0x00400040, ioaddr + RxIntrSel);	/* Interrupt on Rx done */  in yellowfin_open()
601 	iowrite32(0x00400040, ioaddr + RxBranchSel);	/* Branch on Rx error */  in yellowfin_open()
602 	iowrite32(0x00400040, ioaddr + RxWaitSel);	/* Wait on Rx done */  in yellowfin_open()
608 	/* Enable automatic generation of flow control frames, period 0xffff. */  in yellowfin_open()
609 	iowrite32(0x0030FFFF, ioaddr + FlowCtrl);  in yellowfin_open()
614 	if (dev->if_port == 0)  in yellowfin_open()
623 		iowrite16(0x01CF, ioaddr + Cnfg);  in yellowfin_open()
625 		iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */  in yellowfin_open()
626 		iowrite16(0x1018, ioaddr + FrameGap1);  in yellowfin_open()
627 		iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);  in yellowfin_open()
632 	iowrite16(0x81ff, ioaddr + IntrEnb);			/* See enum intr_status_bits */  in yellowfin_open()
633 	iowrite16(0x0000, ioaddr + EventStatus);		/* Clear non-interrupting events */  in yellowfin_open()
634 	iowrite32(0x80008000, ioaddr + RxCtrl);		/* Start Rx and Tx channels. */  in yellowfin_open()
635 	iowrite32(0x80008000, ioaddr + TxCtrl);  in yellowfin_open()
642 	timer_setup(&yp->timer, yellowfin_timer, 0);  in yellowfin_open()
666 		int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);  in yellowfin_timer()
667 		int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);  in yellowfin_timer()
671 				      yp->phys[0], bmsr, lpa);  in yellowfin_timer()
675 		iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);  in yellowfin_timer()
701 		for (i = 0; i < RX_RING_SIZE; i++)  in yellowfin_tx_timeout()
705 		for (i = 0; i < TX_RING_SIZE; i++)  in yellowfin_tx_timeout()
714 	dev->if_port = 0;  in yellowfin_tx_timeout()
717 	iowrite32(0x10001000, yp->base + TxCtrl);  in yellowfin_tx_timeout()
731 	yp->tx_full = 0;  in yellowfin_init_ring()
732 	yp->cur_rx = yp->cur_tx = 0;  in yellowfin_init_ring()
733 	yp->dirty_tx = 0;  in yellowfin_init_ring()
737 	for (i = 0; i < RX_RING_SIZE; i++) {  in yellowfin_init_ring()
744 	for (i = 0; i < RX_RING_SIZE; i++) {  in yellowfin_init_ring()
756 		for (j = 0; j < i; j++)  in yellowfin_init_ring()
766 	for (i = 0; i < TX_RING_SIZE; i++) {  in yellowfin_init_ring()
777 	for (i = 0; i < TX_RING_SIZE; i++) {  in yellowfin_init_ring()
779 		yp->tx_skbuff[i] = 0;  in yellowfin_init_ring()
799 				&(yp->tx_status[0].tx_errs) -  in yellowfin_init_ring()
800 				&(yp->tx_status[0]));  in yellowfin_init_ring()
809 	yp->tx_tail_desc = &yp->tx_status[0];  in yellowfin_init_ring()
810 	return 0;  in yellowfin_init_ring()
831 		if (cacheline_end > 24  || cacheline_end == 0) {  in yellowfin_start_xmit()
846 	yp->tx_ring[entry].result_status = 0;  in yellowfin_start_xmit()
849 		yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);  in yellowfin_start_xmit()
874 		cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :  in yellowfin_start_xmit()
881 	iowrite32(0x10001000, yp->base + TxCtrl);  in yellowfin_start_xmit()
903 	unsigned int handled = 0;  in yellowfin_interrupt()
917 		if (intr_status == 0)  in yellowfin_interrupt()
923 			iowrite32(0x10001000, ioaddr + RxCtrl);		/* Wake Rx engine. */  in yellowfin_interrupt()
927 		for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {  in yellowfin_interrupt()
931 			if (yp->tx_ring[entry].result_status == 0)  in yellowfin_interrupt()
946 			yp->tx_full = 0;  in yellowfin_interrupt()
953 			for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;  in yellowfin_interrupt()
969 				if (tx_errs == 0)  in yellowfin_interrupt()
972 				if (tx_errs & 0xF810) {  in yellowfin_interrupt()
980 					if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;  in yellowfin_interrupt()
981 					if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;  in yellowfin_interrupt()
982 					if (tx_errs & 0x2000) dev->stats.tx_window_errors++;  in yellowfin_interrupt()
983 					if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;  in yellowfin_interrupt()
999 				yp->tx_skbuff[entry] = 0;  in yellowfin_interrupt()
1001 				yp->tx_status[entry].tx_errs = 0;  in yellowfin_interrupt()
1015 				yp->tx_full = 0;  in yellowfin_interrupt()
1025 		if (intr_status & 0x2ee)	/* Abnormal error summary. */  in yellowfin_interrupt()
1028 		if (--boguscnt < 0) {  in yellowfin_interrupt()
1076 			le32_to_cpu(desc->result_status)) & 0xffff;  in yellowfin_rx()
1081 		if (--boguscnt < 0)  in yellowfin_rx()
1087 			if (data_size != 0)  in yellowfin_rx()
1091 		} else if ((yp->drv_flags & IsGigabit)  &&  (frame_status & 0x0038)) {  in yellowfin_rx()
1097 			if (frame_status & 0x0060) dev->stats.rx_length_errors++;  in yellowfin_rx()
1098 			if (frame_status & 0x0008) dev->stats.rx_frame_errors++;  in yellowfin_rx()
1099 			if (frame_status & 0x0010) dev->stats.rx_crc_errors++;  in yellowfin_rx()
1100 			if (frame_status < 0) dev->stats.rx_dropped++;  in yellowfin_rx()
1102 				   ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {  in yellowfin_rx()
1106 			if (status1 & 0xC0) dev->stats.rx_length_errors++;  in yellowfin_rx()
1107 			if (status2 & 0x03) dev->stats.rx_frame_errors++;  in yellowfin_rx()
1108 			if (status2 & 0x04) dev->stats.rx_crc_errors++;  in yellowfin_rx()
1109 			if (status2 & 0x80) dev->stats.rx_dropped++;  in yellowfin_rx()
1118 			if (bogus_rx++ == 0)  in yellowfin_rx()
1163 	for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {  in yellowfin_rx()
1177 		yp->rx_ring[entry].result_status = 0;	/* Clear complete bit. */  in yellowfin_rx()
1178 		if (entry != 0)  in yellowfin_rx()
1187 	return 0;  in yellowfin_rx()
1219 	iowrite16(0x0000, ioaddr + IntrEnb);  in yellowfin_close()
1222 	iowrite32(0x80000000, ioaddr + RxCtrl);  in yellowfin_close()
1223 	iowrite32(0x80000000, ioaddr + TxCtrl);  in yellowfin_close()
1231 		for (i = 0; i < TX_RING_SIZE*2; i++)  in yellowfin_close()
1237 		for (i = 0; i < TX_RING_SIZE; i++)  in yellowfin_close()
1244 		for (i = 0; i < RX_RING_SIZE; i++) {  in yellowfin_close()
1250 				if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {  in yellowfin_close()
1254 					for (j = 0; j < 0x50; j++)  in yellowfin_close()
1267 	for (i = 0; i < RX_RING_SIZE; i++) {  in yellowfin_close()
1269 		yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */  in yellowfin_close()
1275 	for (i = 0; i < TX_RING_SIZE; i++) {  in yellowfin_close()
1281 	if (yellowfin_debug > 0) {  in yellowfin_close()
1287 	return 0;  in yellowfin_close()
1299 	iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);  in set_rx_mode()
1301 		iowrite16(0x000F, ioaddr + AddrMode);  in set_rx_mode()
1305 		iowrite16(0x000B, ioaddr + AddrMode);  in set_rx_mode()
1311 		memset(hash_table, 0, sizeof(hash_table));  in set_rx_mode()
1318 				bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;  in set_rx_mode()
1320 				bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;  in set_rx_mode()
1322 				bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;  in set_rx_mode()
1325 			bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;  in set_rx_mode()
1329 		for (i = 0; i < 4; i++)  in set_rx_mode()
1331 		iowrite16(0x0003, ioaddr + AddrMode);  in set_rx_mode()
1333 		iowrite16(0x0001, ioaddr + AddrMode);  in set_rx_mode()
1336 	iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);  in set_rx_mode()
1360 		data->phy_id = np->phys[0] & 0x1f;  in netdev_ioctl()
1364 		data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);  in netdev_ioctl()
1365 		return 0;  in netdev_ioctl()
1368 		if (data->phy_id == np->phys[0]) {  in netdev_ioctl()
1371 			case 0:  in netdev_ioctl()
1373 				np->medialock = (value & 0x9000) ? 0 : 1;  in netdev_ioctl()
1375 					np->full_duplex = (value & 0x0100) ? 1 : 0;  in netdev_ioctl()
1381 		mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);  in netdev_ioctl()
1382 		return 0;  in netdev_ioctl()