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/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c19 #define PLL_IDIV_REG 0x0
20 #define PLL_FBDIV_REG 0x4
21 #define PLL_ODIV0_REG 0x8
22 #define PLL_ODIV1_REG 0xC
34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/drivers/crypto/intel/qat/qat_420xx/
H A Dadf_420xx_hw_data.h10 #define ADF_420XX_ACCELENGINES_MASK 0x1FFFF
11 #define ADF_420XX_ADMIN_AE_MASK 0x10000
13 #define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK (0xFF)
14 #define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK (0xFF00FF)
15 #define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK (0x10001)
16 #define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK (0xF0007)
17 #define ADF_420XX_PARITYERRORMASK_PKE_MASK (0xFFF)
18 #define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK (0x3FF03FF)
/linux/drivers/crypto/intel/qat/qat_4xxx/
H A Dadf_4xxx_hw_data.h11 #define ADF_4XXX_ACCELENGINES_MASK (0x1FF)
12 #define ADF_4XXX_ADMIN_AE_MASK (0x100)
14 #define ADF_4XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1F
15 #define ADF_4XXX_PARITYERRORMASK_ATH_CPH_MASK 0xF000F
16 #define ADF_4XXX_PARITYERRORMASK_CPR_XLT_MASK 0x10001
17 #define ADF_4XXX_PARITYERRORMASK_DCPR_UCS_MASK 0x30007
18 #define ADF_4XXX_PARITYERRORMASK_PKE_MASK 0x3F
/linux/drivers/thermal/
H A Drockchip_thermal.c29 TSHUT_MODE_CRU = 0,
36 * 0: low active, 1: high active
39 TSHUT_LOW_ACTIVE = 0,
49 ADC_DECREMENT = 0,
75 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
76 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
189 #define TSADCV2_USER_CON 0x00
190 #define TSADCV2_AUTO_CON 0x04
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_plane_helper_test.c20 DRM_MODE("1024x768", 0, 65000, 1024, 1048,
21 1184, 1344, 0, 768, 771, 777, 806, 0,
79 return 0; in drm_plane_helper_init()
88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
89 "src x coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
93 "src y coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
122 0, params->msg); in drm_test_check_plane_state()
140 .src = { 0, 0,
143 .crtc = { 0, 0, 2048, 2048 },
[all …]
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c22 /* offset=0 */
25 "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
27 "l1-dcache-load\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
29 "l1-dcache-load-refs\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
31 "l1-dcache-load-reference\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
33 "l1-dcache-load-ops\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
35 "l1-dcache-load-access\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
37 "l1-dcache-load-misses\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00000\000\000\000\000\000"
39 "l1-dcache-load-miss\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00010\000\000\000\000\000"
41 "l1-dcache-loads\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\00
[all...]
/linux/tools/include/linux/
H A Darm-smccc.h18 #define ARM_SMCCC_STD_CALL _AC(0,U)
22 #define ARM_SMCCC_SMC_32 0
26 #define ARM_SMCCC_OWNER_MASK 0x3F
29 #define ARM_SMCCC_FUNC_MASK 0xFFFF
45 #define ARM_SMCCC_OWNER_ARCH 0
57 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
59 #define ARM_SMCCC_QUIRK_NONE 0
62 #define ARM_SMCCC_VERSION_1_0 0x10000
63 #define ARM_SMCCC_VERSION_1_1 0x10001
64 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cfg-afdo.c36 .val32 = 0x20001,
42 .val32 = 0x20002,
44 /* strobe window counter 0 - reload from param 0 */
47 .offset = TRCCNTVRn(0),
52 .offset = TRCCNTRLDVRn(0),
54 .val32 = 0,
58 .offset = TRCCNTCTLRn(0),
60 .val32 = 0x10001,
78 .val32 = 0x8102,
83 .offset = TRCSEQEVRn(0),
[all …]
/linux/drivers/media/platform/qcom/venus/
H A Dhfi_cmds.h12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
/linux/include/uapi/linux/
H A Ddlmconstants.h31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
140 #define DLM_LKF_NOQUEUE 0x00000001
141 #define DLM_LKF_CANCEL 0x00000002
142 #define DLM_LKF_CONVERT 0x00000004
143 #define DLM_LKF_VALBLK 0x00000008
144 #define DLM_LKF_QUECVT 0x00000010
145 #define DLM_LKF_IVVALBLK 0x00000020
146 #define DLM_LKF_CONVDEADLK 0x00000040
147 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
H A Dvboxguest.h17 #define VBG_IOCTL_HDR_VERSION 0x10001
19 #define VBG_IOCTL_HDR_TYPE_DEFAULT 0
56 #define VBG_IOC_VERSION 0x00010000u
86 /** The SVN revision of the driver, or 0. */
98 _IOWR('V', 0, struct vbg_ioctl_driver_version_info)
277 #define VBGL_IOC_AGC_FLAGS_CONFIG_ACQUIRE_MODE 0x00000001
278 #define VBGL_IOC_AGC_FLAGS_VALID_MASK 0x00000001
/linux/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dxtensa.c31 int c = 0; in nvkm_xtensa_oclass_get()
47 return nvkm_gpuobj_new(object->engine->subdev.device, 0x10000, align, in nvkm_xtensa_cclass_bind()
63 u32 unk104 = nvkm_rd32(device, base + 0xd04); in nvkm_xtensa_intr()
64 u32 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
65 u32 chan = nvkm_rd32(device, base + 0xc28); in nvkm_xtensa_intr()
66 u32 unk10c = nvkm_rd32(device, base + 0xd0c); in nvkm_xtensa_intr()
68 if (intr & 0x10) in nvkm_xtensa_intr()
70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
71 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
72 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { in nvkm_xtensa_intr()
[all …]
/linux/arch/x86/include/asm/uv/
H A Dbios.h32 #define UV_BIOS_EXTRA 0x10000
33 #define UV_BIOS_GET_PCI_TOPOLOGY 0x10001
34 #define UV_BIOS_GET_GEOINFO 0x10003
36 #define UV_BIOS_EXTRA_OP_MEM_COPYIN 0x1000
37 #define UV_BIOS_EXTRA_OP_MEM_COPYOUT 0x2000
38 #define UV_BIOS_EXTRA_OP_MASK 0x0fff
51 BIOS_STATUS_SUCCESS = 0,
69 #define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */
97 #define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */
98 #define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */
[all …]
/linux/tools/perf/pmu-events/arch/x86/clearwaterforest/
H A Dcache.json4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x31",
12 "Counter": "0,1,2,3,4,5,6,7",
13 "EventCode": "0x30",
20 "Counter": "0,1,2,3,4,5,6,7",
21 "EventCode": "0x24",
24 "UMask": "0x1ff"
28 "Counter": "0,1,2,3,4,5,6,7",
29 "EventCode": "0x24",
32 "UMask": "0xc
2 { global() object
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8956-sony-xperia-loire.dtsi16 qcom,msm-id = <266 0x10001>; /* MSM8956 v1.1 */
17 qcom,board-id = <8 0>;
32 reg = <0x0 0x83000000 0x0 0x2800000>;
37 reg = <0 0x57f00000 0 0x100000>;
38 record-size = <0x20000>;
39 console-size = <0x40000>;
40 ftrace-size = <0x20000>;
41 pmsg-size = <0x20000>;
111 /* Cluster 0 supply */
274 gpio-reserved-ranges = <0 4>;
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dsdio.h13 #define SDIOD_FBR_SIZE 0x100
16 #define SDIO_FUNC_ENABLE_1 0x02
17 #define SDIO_FUNC_ENABLE_2 0x04
20 #define SDIO_FUNC_READY_1 0x02
21 #define SDIO_FUNC_READY_2 0x04
24 #define INTR_STATUS_FUNC1 0x2
25 #define INTR_STATUS_FUNC2 0x4
28 #define REG_F0_REG_MASK 0x7FF
29 #define REG_F1_MISC_MASK 0x1FFFF
31 /* function 0 vendor specific CCCR registers */
[all …]
/linux/drivers/virt/vboxguest/
H A Dvmmdev.h17 #define VMMDEV_PORT_OFF_REQUEST 0
50 #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
72 #define VMMDEV_EVENT_VALID_EVENT_MASK 0x000007ffU
79 #define VMMDEV_VERSION 0x00010004
81 #define VMMDEV_VERSION_MINOR (VMMDEV_VERSION & 0xffff)
87 #define VMMDEV_REQUEST_HEADER_VERSION 0x10001
124 #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
155 #define VMMDEV_MOUSE_RANGE_MIN 0
157 #define VMMDEV_MOUSE_RANGE_MAX 0xFFFF
181 #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_offset.h28 // base address: 0x11a08000
29 …O_HWDID 0x2270800
30 …e regDXIO_HWDID_BASE_IDX 0
31 …O_LINKAGE_LANEGRP 0x2270802
32 …e regDXIO_LINKAGE_LANEGRP_BASE_IDX 0
33 …O_LINKAGE_KPDMX 0x2270803
34 …e regDXIO_LINKAGE_KPDMX_BASE_IDX 0
35 …O_LINKAGE_KPMX 0x2270804
36 …O_LINKAGE_KPFIFO 0x2270805
37 …O_LINKAGE_KPNP 0x2270806
[all …]
/linux/drivers/mmc/host/
H A Dsdricoh_cs.c33 #define SDRICOH_PCI_REGION 0
34 #define SDRICOH_PCI_REGION_SIZE 0x1000
37 #define R104_VERSION 0x104
38 #define R200_CMD 0x200
39 #define R204_CMD_ARG 0x204
40 #define R208_DATAIO 0x208
41 #define R20C_RESP 0x20c
42 #define R21C_STATUS 0x21c
43 #define R2E0_INIT 0x2e0
44 #define R2E4_STATUS_RESP 0x2e4
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gen7_2_0_snapshot.h99 {A7XX_TP0_TMO_DATA, 0x200, 6, 2, PIPE_BR, A7XX_USPTP},
100 {A7XX_TP0_SMO_DATA, 0x80, 6, 2, PIPE_BR, A7XX_USPTP},
101 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, PIPE_BR, A7XX_USPTP},
102 {A7XX_SP_INST_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
103 {A7XX_SP_INST_DATA_1, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
104 {A7XX_SP_LB_0_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
105 {A7XX_SP_LB_1_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
106 {A7XX_SP_LB_2_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
107 {A7XX_SP_LB_3_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
108 {A7XX_SP_LB_4_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP},
[all …]
H A Dadreno_gen7_0_0_snapshot.h85 {A7XX_TP0_TMO_DATA, 0x200, 4, 2, PIPE_BR, A7XX_USPTP},
86 {A7XX_TP0_SMO_DATA, 0x80, 4, 2, PIPE_BR, A7XX_USPTP},
87 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, PIPE_BR, A7XX_USPTP},
88 {A7XX_SP_INST_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
89 {A7XX_SP_INST_DATA_1, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
90 {A7XX_SP_LB_0_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
91 {A7XX_SP_LB_1_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
92 {A7XX_SP_LB_2_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
93 {A7XX_SP_LB_3_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
94 {A7XX_SP_LB_4_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP},
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dcache.json4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x31",
12 "Counter": "0,1,2,3,4,5,6,7",
13 "EventCode": "0x51",
17 "UMask": "0x1"
21 "Counter": "0,1,2,3,4,5,6,7",
22 "EventCode": "0x25",
26 "UMask": "0x4"
30 "Counter": "0,1,2,3,4,5,6,7",
31 "EventCode": "0x2
2 { global() object
[all...]
/linux/drivers/media/platform/st/stm32/dma2d/
H A Ddma2d.c86 .line_offset = 0,
87 .a_rgb = {0x00, 0x00, 0x00, 0xff},
89 .fmt = (struct dma2d_fmt *)&formats[0],
97 for (i = 0; i < NUM_FORMATS; i++) { in find_fmt()
119 return sizes[0] < f->size ? -EINVAL : 0; in dma2d_queue_setup()
121 sizes[0] = f->size; in dma2d_queue_setup()
124 return 0; in dma2d_queue_setup()
136 return 0; in dma2d_buf_out_validate()
144 if (vb2_plane_size(vb, 0) < f->size) in dma2d_buf_prepare()
147 vb2_set_plane_payload(vb, 0, f->size); in dma2d_buf_prepare()
[all …]

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