| /linux/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 19 #define PLL_IDIV_REG 0x0
20 #define PLL_FBDIV_REG 0x4
21 #define PLL_ODIV0_REG 0x8
22 #define PLL_ODIV1_REG 0xC
34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
|
| /linux/arch/riscv/boot/dts/allwinner/ |
| H A D | sun20i-d1s.dtsi | 12 #size-cells = <0>;
14 cpu0: cpu@0 {
17 reg = <0>;
60 reg = <0x6011000 0x20>;
69 reg = <0x10000000 0x4000000>;
74 #address-cells = <0>;
82 <0x00003 0x00003 0x00000008>,
83 <0x00004 0x00004 0x00000010>,
84 <0x00005 0x00005 0x00000200>,
85 <0x00006 0x00006 0x00000100>,
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xB7",
7 "MSRIndex": "0x1a6,0x1a7",
8 "MSRValue": "0x10001",
10 "UMask": "0x1",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x2A,0x2B",
18 "MSRIndex": "0x1a6,0x1a7",
19 "MSRValue": "0x10001",
21 "UMask": "0x1",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xc1",
8 "UMask": "0x8",
13 "Counter": "0,1,2,3,4,5,6,7",
15 "EventCode": "0xe4",
18 "UMask": "0x1",
23 "Counter": "0,1,2,3,4,5,6,7",
24 "EventCode": "0xB7",
26 "MSRIndex": "0x1a6,0x1a7",
27 "MSRValue": "0x10001",
[all …]
|
| /linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
|
| /linux/drivers/thermal/ |
| H A D | rockchip_thermal.c | 28 TSHUT_MODE_CRU = 0,
35 * 0: low active, 1: high active
38 TSHUT_LOW_ACTIVE = 0,
48 ADC_DECREMENT = 0,
73 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
74 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
136 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
137 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
164 #define TSADCV2_USER_CON 0x00
165 #define TSADCV2_AUTO_CON 0x04
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xc1",
8 "UMask": "0x4",
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0xc1",
17 "UMask": "0x8",
22 "Counter": "0,1,2,3",
23 "EventCode": "0x28",
26 "UMask": "0x2",
31 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
6 "EventCode": "0xe4",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0xB7",
16 "MSRIndex": "0x1a6,0x1a7",
17 "MSRValue": "0x10001",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3,4,5,6,7",
24 "EventCode": "0xB7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
6 "EventCode": "0xe4",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0xB7",
16 "MSRIndex": "0x1a6,0x1a7",
17 "MSRValue": "0x10001",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3,4,5,6,7",
24 "EventCode": "0xB7",
[all …]
|
| /linux/drivers/crypto/intel/qat/qat_420xx/ |
| H A D | adf_420xx_hw_data.h | 10 #define ADF_420XX_ACCELENGINES_MASK 0x1FFFF
11 #define ADF_420XX_ADMIN_AE_MASK 0x10000
13 #define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK (0xFF)
14 #define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK (0xFF00FF)
15 #define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK (0x10001)
16 #define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK (0xF0007)
17 #define ADF_420XX_PARITYERRORMASK_PKE_MASK (0xFFF)
18 #define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK (0x3FF03FF)
|
| /linux/drivers/crypto/intel/qat/qat_4xxx/ |
| H A D | adf_4xxx_hw_data.h | 11 #define ADF_4XXX_ACCELENGINES_MASK (0x1FF)
12 #define ADF_4XXX_ADMIN_AE_MASK (0x100)
14 #define ADF_4XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1F
15 #define ADF_4XXX_PARITYERRORMASK_ATH_CPH_MASK 0xF000F
16 #define ADF_4XXX_PARITYERRORMASK_CPR_XLT_MASK 0x10001
17 #define ADF_4XXX_PARITYERRORMASK_DCPR_UCS_MASK 0x30007
18 #define ADF_4XXX_PARITYERRORMASK_PKE_MASK 0x3F
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5",
6 "EventCode": "0xe4",
10 "UMask": "0x1"
14 "Counter": "0,1,2,3,4,5",
15 "EventCode": "0xB7",
17 "MSRIndex": "0x1a6,0x1a7",
18 "MSRValue": "0x10008",
20 "UMask": "0x1"
24 "Counter": "0,1,2,3,4,5",
25 "EventCode": "0xB7",
[all …]
|
| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_plane_helper_test.c | 20 DRM_MODE("1024x768", 0, 65000, 1024, 1048,
21 1184, 1344, 0, 768, 771, 777, 806, 0,
79 return 0; in drm_plane_helper_init()
88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
89 "src x coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
93 "src y coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
122 0, params->msg); in drm_test_check_plane_state()
140 .src = { 0, 0,
143 .crtc = { 0, 0, 2048, 2048 },
[all …]
|
| /linux/arch/riscv/boot/dts/thead/ |
| H A D | th1520.dtsi | 17 #size-cells = <0>;
20 c910_0: cpu@0 {
27 reg = <0>;
129 <0x00003 0x00003 0x0007fff8>,
130 <0x00004 0x00004 0x0007fff8>,
131 <0x00005 0x00005 0x0007fff8>,
132 <0x00006 0x00006 0x0007fff8>,
133 <0x00007 0x00007 0x0007fff8>,
134 <0x00008 0x00008 0x0007fff8>,
135 <0x00009 0x00009 0x0007fff8>,
[all …]
|
| /linux/tools/include/linux/ |
| H A D | arm-smccc.h | 18 #define ARM_SMCCC_STD_CALL _AC(0,U)
22 #define ARM_SMCCC_SMC_32 0
26 #define ARM_SMCCC_OWNER_MASK 0x3F
29 #define ARM_SMCCC_FUNC_MASK 0xFFFF
45 #define ARM_SMCCC_OWNER_ARCH 0
57 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
59 #define ARM_SMCCC_QUIRK_NONE 0
62 #define ARM_SMCCC_VERSION_1_0 0x10000
63 #define ARM_SMCCC_VERSION_1_1 0x10001
64 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
|
| /linux/arch/x86/include/asm/shared/ |
| H A D | tdx.h | 8 #define TDX_HYPERCALL_STANDARD 0
10 #define TDX_CPUID_LEAF_ID 0x21
14 #define TDG_VP_VMCALL 0
22 #define TDCS_NOTIFY_ENABLES 0x9100000000000010
25 #define TDVMCALL_MAP_GPA 0x10001
26 #define TDVMCALL_GET_QUOTE 0x10002
27 #define TDVMCALL_REPORT_FATAL_ERROR 0x10003
59 #define TDX_PS_4K 0
|
| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-cfg-afdo.c | 36 .val32 = 0x20001,
42 .val32 = 0x20002,
44 /* strobe window counter 0 - reload from param 0 */
47 .offset = TRCCNTVRn(0),
52 .offset = TRCCNTRLDVRn(0),
54 .val32 = 0,
58 .offset = TRCCNTCTLRn(0),
60 .val32 = 0x10001,
78 .val32 = 0x8102,
83 .offset = TRCSEQEVRn(0),
[all …]
|
| /linux/drivers/media/platform/qcom/venus/ |
| H A D | hfi_cmds.h | 12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | cpus.yaml | 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
|
| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | dlmconstants.h | 31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
140 #define DLM_LKF_NOQUEUE 0x00000001
141 #define DLM_LKF_CANCEL 0x00000002
142 #define DLM_LKF_CONVERT 0x00000004
143 #define DLM_LKF_VALBLK 0x00000008
144 #define DLM_LKF_QUECVT 0x00000010
145 #define DLM_LKF_IVVALBLK 0x00000020
146 #define DLM_LKF_CONVDEADLK 0x00000040
147 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | other.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0xc1",
8 "UMask": "0x8"
12 "Counter": "0,1,2,3,4,5,6,7",
13 "EventCode": "0xb7",
16 "UMask": "0x2"
20 "Counter": "0,1,2,3",
21 "EventCode": "0x2A,0x2B",
23 "MSRIndex": "0x1a6,0x1a7",
24 "MSRValue": "0x10004",
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ |
| H A D | xtensa.c | 31 int c = 0; in nvkm_xtensa_oclass_get()
47 return nvkm_gpuobj_new(object->engine->subdev.device, 0x10000, align, in nvkm_xtensa_cclass_bind()
63 u32 unk104 = nvkm_rd32(device, base + 0xd04); in nvkm_xtensa_intr()
64 u32 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
65 u32 chan = nvkm_rd32(device, base + 0xc28); in nvkm_xtensa_intr()
66 u32 unk10c = nvkm_rd32(device, base + 0xd0c); in nvkm_xtensa_intr()
68 if (intr & 0x10) in nvkm_xtensa_intr()
70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
71 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
72 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { in nvkm_xtensa_intr()
[all …]
|
| /linux/arch/x86/include/asm/uv/ |
| H A D | bios.h | 32 #define UV_BIOS_EXTRA 0x10000
33 #define UV_BIOS_GET_PCI_TOPOLOGY 0x10001
34 #define UV_BIOS_GET_GEOINFO 0x10003
36 #define UV_BIOS_EXTRA_OP_MEM_COPYIN 0x1000
37 #define UV_BIOS_EXTRA_OP_MEM_COPYOUT 0x2000
38 #define UV_BIOS_EXTRA_OP_MASK 0x0fff
51 BIOS_STATUS_SUCCESS = 0,
69 #define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */
97 #define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */
98 #define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | other.json | 4 "Counter": "0,1,2,3",
7 "EventCode": "0x63",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x63",
18 "UMask": "0x2"
22 "Counter": "0,1,2,3",
24 "EventCode": "0x63",
27 "UMask": "0x2"
31 "Counter": "0,1,2,3",
33 "EventCode": "0x63",
[all …]
|