Home
last modified time | relevance | path

Searched +full:0 +full:x0d00 (Results 1 – 25 of 104) sorted by relevance

12345

/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
16 #clock-cells = <0>;
19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>;
26 #clock-cells = <0>;
29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>;
35 #clock-cells = <0>;
38 ti,bit-shift = <0xc>;
[all …]
H A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
18 reg = <0x0d40>;
22 #clock-cells = <0>;
27 reg = <0x1270>;
32 #clock-cells = <0>;
35 reg = <0x0d70>;
40 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_service.c25 RPM_CONFIG0, /* _MMIO(0x0d00) */
26 MIRROR_FUSE3, /* _MMIO(0x9118) */
27 XELP_EU_ENABLE, /* _MMIO(0x9134) */
28 XELP_GT_SLICE_ENABLE, /* _MMIO(0x9138) */
29 XELP_GT_GEOMETRY_DSS_ENABLE, /* _MMIO(0x913c) */
30 GT_VEBOX_VDBOX_DISABLE, /* _MMIO(0x9140) */
31 HUC_KERNEL_LOAD_INFO, /* _MMIO(0xc1dc) */
35 RPM_CONFIG0, /* _MMIO(0x0d00) */
36 MIRROR_FUSE3, /* _MMIO(0x9118) */
37 MIRROR_FUSE1, /* _MMIO(0x911c) */
[all …]
/linux/drivers/net/ethernet/qualcomm/
H A Dqca_7k.h21 #define QCA7K_SPI_WRITE (0 << 15)
23 #define QCA7K_SPI_EXTERNAL (0 << 14)
27 #define QCASPI_HW_BUF_LEN 0xC5B
30 #define SPI_REG_BFR_SIZE 0x0100
31 #define SPI_REG_WRBUF_SPC_AVA 0x0200
32 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
33 #define SPI_REG_SPI_CONFIG 0x0400
34 #define SPI_REG_SPI_STATUS 0x0500
35 #define SPI_REG_INTR_CAUSE 0x0C00
36 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Ddos_regs.h11 #define VDEC_ASSIST_AMR1_INT8 0x00b4
13 #define ASSIST_MBOX1_CLR_REG 0x01d4
14 #define ASSIST_MBOX1_MASK 0x01d8
16 #define MPSR 0x0c04
17 #define MCPU_INTR_MSK 0x0c10
18 #define CPSR 0x0c84
20 #define IMEM_DMA_CTRL 0x0d00
21 #define IMEM_DMA_ADR 0x0d04
22 #define IMEM_DMA_COUNT 0x0d08
23 #define LMEM_DMA_CTRL 0x0d40
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
H A Dprcm-common.h22 #define OCP_MOD 0x000
23 #define MPU_MOD 0x100
24 #define CORE_MOD 0x200
25 #define GFX_MOD 0x300
26 #define WKUP_MOD 0x400
27 #define PLL_MOD 0x500
32 #define OMAP24XX_DSP_MOD 0x800
34 #define OMAP2430_MDM_MOD 0xc00
37 #define OMAP3430_IVA2_MOD -0x800
40 #define OMAP3430_DSS_MOD 0x600
[all …]
/linux/drivers/media/pci/smipcie/
H A Dsmipcie.h31 #define MSI_CONTROL_REG_BASE 0x0800
32 #define SYSTEM_CONTROL_REG_BASE 0x0880
33 #define PCIE_EP_DEBUG_REG_BASE 0x08C0
34 #define IR_CONTROL_REG_BASE 0x0900
35 #define I2C_A_CONTROL_REG_BASE 0x0940
36 #define I2C_B_CONTROL_REG_BASE 0x0980
37 #define ATV_PORTA_CONTROL_REG_BASE 0x09C0
38 #define DTV_PORTA_CONTROL_REG_BASE 0x0A00
39 #define AES_PORTA_CONTROL_REG_BASE 0x0A80
40 #define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
[all …]
/linux/sound/soc/codecs/
H A Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/linux/arch/m68k/include/asm/
H A Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
H A Dm523xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
H A Dm528xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
H A Dm527xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h18 #define NFP_NET_APP_CAP_SP_INDIFF BIT_ULL(0) /* indifferent to port speed */
40 #define NFP_NET_META_VLAN_TCI_MASK GENMASK(15, 0)
53 #define NFP_META_PORT_ID_CTRL ~0U
62 #define NFP_NET_RSS_NONE 0
80 /* Read/Write config words (0x0000 - 0x002c)
94 #define NFP_NET_CFG_CTRL 0x0000
95 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
96 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
97 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
98 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux/arch/powerpc/boot/
H A Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/linux/include/uapi/linux/
H A Din6.h83 #define IPV6_FL_A_GET 0
92 #define IPV6_FL_S_NONE 0
107 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
108 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
111 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
112 #define IPV6_PRIORITY_FILLER 0x0100
113 #define IPV6_PRIORITY_UNATTENDED 0x0200
114 #define IPV6_PRIORITY_RESERVED1 0x0300
115 #define IPV6_PRIORITY_BULK 0x0400
116 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
/linux/include/linux/
H A Dbrcmphy.h12 #define PHY_ID_BCM50610 0x0143bd60
13 #define PHY_ID_BCM50610M 0x0143bd70
14 #define PHY_ID_BCM5221 0x004061e0
15 #define PHY_ID_BCM5241 0x0143bc30
16 #define PHY_ID_BCMAC131 0x0143bc70
17 #define PHY_ID_BCM5481 0x0143bca0
18 #define PHY_ID_BCM5395 0x0143bcf0
19 #define PHY_ID_BCM53125 0x03625f20
20 #define PHY_ID_BCM53128 0x03625e10
21 #define PHY_ID_BCM54810 0x03625d00
[all …]
/linux/arch/arm/mach-imx/
H A Dtzic.c28 #define TZIC_INTCNTL 0x0000 /* Control register */
29 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
30 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
31 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
32 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
33 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
34 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
35 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
36 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
37 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
[all …]
/linux/drivers/irqchip/
H A Dirq-davinci-cp-intc.c22 #define DAVINCI_CP_INTC_CTRL 0x04
23 #define DAVINCI_CP_INTC_HOST_CTRL 0x0c
24 #define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
25 #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
26 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
27 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
28 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
29 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
30 #define DAVINCI_CP_INTC_PRIO_IDX 0x80
31 #define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
[all …]
/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/linux/drivers/media/usb/as102/
H A Das10x_cmd.h18 #define SERVICE_PROG_ID 0x0002
19 #define SERVICE_PROG_VERSION 0x0001
21 #define HIER_NONE 0x00
22 #define HIER_LOW_PRIORITY 0x01
31 #define CFG_MODE_ODSP_RESUME 0
35 #define DUMP_BLOCK_SIZE_MAX 0x20
41 CONTROL_PROC_TURNON = 0x0001,
42 CONTROL_PROC_TURNON_RSP = 0x0100,
43 CONTROL_PROC_SET_REGISTER = 0x0002,
44 CONTROL_PROC_SET_REGISTER_RSP = 0x0200,
[all …]
/linux/drivers/w1/masters/
H A Damd_axi_w1.c24 #define AXIW1_IPID 0x10ee4453
26 #define AXIW1_INST_REG 0x0
27 #define AXIW1_CTRL_REG 0x4
28 #define AXIW1_IRQE_REG 0x8
29 #define AXIW1_STAT_REG 0xC
30 #define AXIW1_DATA_REG 0x10
31 #define AXIW1_IPVER_REG 0x18
32 #define AXIW1_IPID_REG 0x1C
34 #define AXIW1_INITPRES 0x0800
35 #define AXIW1_READBIT 0x0C00
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]

12345