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/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/linux/arch/m68k/include/asm/
H A Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/linux/sound/soc/codecs/
H A Drt1019.h11 #define RT1019_DEVICE_ID_VAL 0x1019
12 #define RT1019_DEVICE_ID_VAL2 0x6731
14 #define RT1019_RESET 0x0000
15 #define RT1019_IDS_CTRL 0x0011
16 #define RT1019_ASEL_CTRL 0x0013
17 #define RT1019_PWR_STRP_2 0x0019
18 #define RT1019_BEEP_TONE 0x001b
19 #define RT1019_VER_ID 0x005c
20 #define RT1019_VEND_ID_1 0x005e
21 #define RT1019_VEND_ID_2 0x005f
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux/sound/pci/cs46xx/
H A Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/include/uapi/linux/
H A Din6.h83 #define IPV6_FL_A_GET 0
92 #define IPV6_FL_S_NONE 0
107 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
108 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
111 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
112 #define IPV6_PRIORITY_FILLER 0x0100
113 #define IPV6_PRIORITY_UNATTENDED 0x0200
114 #define IPV6_PRIORITY_RESERVED1 0x0300
115 #define IPV6_PRIORITY_BULK 0x0400
116 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_adminq_cmd.h15 #define IAVF_FW_API_VERSION_MAJOR 0x0001
16 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005
17 #define IAVF_FW_API_VERSION_MINOR_X710 0x0008
24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 iavf_aqc_opc_get_version = 0x0001,
30 iavf_aqc_opc_driver_version = 0x0002,
31 iavf_aqc_opc_queue_shutdown = 0x0003,
32 iavf_aqc_opc_set_pf_context = 0x0004,
35 iavf_aqc_opc_request_resource = 0x0008,
36 iavf_aqc_opc_release_resource = 0x0009,
[all …]
/linux/drivers/media/pci/smipcie/
H A Dsmipcie.h31 #define MSI_CONTROL_REG_BASE 0x0800
32 #define SYSTEM_CONTROL_REG_BASE 0x0880
33 #define PCIE_EP_DEBUG_REG_BASE 0x08C0
34 #define IR_CONTROL_REG_BASE 0x0900
35 #define I2C_A_CONTROL_REG_BASE 0x0940
36 #define I2C_B_CONTROL_REG_BASE 0x0980
37 #define ATV_PORTA_CONTROL_REG_BASE 0x09C0
38 #define DTV_PORTA_CONTROL_REG_BASE 0x0A00
39 #define AES_PORTA_CONTROL_REG_BASE 0x0A80
40 #define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm281xx.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .trig = TRIGGER(0x0e04, 0),
18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .sel = SELECTOR(0x0a04, 0, 2),
48 .div = DIVIDER(0x0a04, 3, 4),
49 .trig = TRIGGER(0x0a40, 0),
[all …]
/linux/drivers/media/usb/as102/
H A Das10x_cmd.h18 #define SERVICE_PROG_ID 0x0002
19 #define SERVICE_PROG_VERSION 0x0001
21 #define HIER_NONE 0x00
22 #define HIER_LOW_PRIORITY 0x01
31 #define CFG_MODE_ODSP_RESUME 0
35 #define DUMP_BLOCK_SIZE_MAX 0x20
41 CONTROL_PROC_TURNON = 0x0001,
42 CONTROL_PROC_TURNON_RSP = 0x0100,
43 CONTROL_PROC_SET_REGISTER = 0x0002,
44 CONTROL_PROC_SET_REGISTER_RSP = 0x0200,
[all …]
/linux/drivers/input/joystick/
H A Dxpad.c80 #define MAP_DPAD_TO_BUTTONS BIT(0)
91 #define XTYPE_XBOX 0
102 #define PKT_XB 0
108 #define FLAG_DELAY_INIT BIT(0)
135 { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
136 { 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 },
137 { 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 },
138 { 0x03f0, 0x038D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wired */
139 { 0x03f0, 0x048D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wireless */
140 { 0x03f0, 0x0495, "HyperX Clutch Gladiate", 0, XTYPE_XBOXONE },
[all …]
/linux/sound/firewire/motu/
H A Dmotu-stream.c12 #define ISOC_COMM_CONTROL_OFFSET 0x0b00
13 #define ISOC_COMM_CONTROL_MASK 0xffff0000
14 #define CHANGE_RX_ISOC_COMM_STATE 0x80000000
15 #define RX_ISOC_COMM_IS_ACTIVATED 0x40000000
16 #define RX_ISOC_COMM_CHANNEL_MASK 0x3f000000
18 #define CHANGE_TX_ISOC_COMM_STATE 0x00800000
19 #define TX_ISOC_COMM_IS_ACTIVATED 0x00400000
20 #define TX_ISOC_COMM_CHANNEL_MASK 0x003f0000
23 #define PACKET_FORMAT_OFFSET 0x0b1
[all...]
H A Dmotu-protocol-v1.c10 // Status register for MOTU 828 (0x'ffff'f000'0b00).
12 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
13 // 0x00008000: mode of optical input interface.
14 // 0x00008000: for S/PDIF signal.
15 // 0x00000000: disabled or for ADAT signal.
16 // 0x00004000: mode of optical output interface.
17 // 0x00004000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00003f00: monitor input mode.
20 // 0x00000800: analog-1/2
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-reg.h12 #define ADDR_IMEM 0x10000
13 #define ADDR_DMEM 0x20000
16 #define APB_CTRL 0
17 #define XT_INT_CTRL 0x04
18 #define MAILBOX_FULL_ADDR 0x08
19 #define MAILBOX_EMPTY_ADDR 0x0c
20 #define MAILBOX0_WR_DATA 0x10
21 #define MAILBOX0_RD_DATA 0x14
22 #define KEEP_ALIVE 0x18
23 #define VER_L 0x1c
[all …]

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