Home
last modified time | relevance | path

Searched +full:0 +full:x0b00 (Results 1 – 25 of 30) sorted by relevance

12

/illumos-gate/usr/src/uts/common/sys/
H A Dxti_osi.h52 #define T_CLASS0 0
63 #define T_PRITOP 0
126 #define ISO_TP 0x0100
132 #define TCO_THROUGHPUT 0x0001
133 #define TCO_TRANSDEL 0x0002
134 #define TCO_RESERRORRATE 0x0003
135 #define TCO_TRANSFFAILPROB 0x0004
136 #define TCO_ESTFAILPROB 0x0005
137 #define TCO_RELFAILPROB 0x0006
138 #define TCO_ESTDELAY 0x0007
[all …]
/illumos-gate/usr/src/lib/iconv_modules/hi_IN/include/
H A Discii.h40 if ( ucs >= 0x0900 && ucs <= 0x097f ) \
42 else if ( ucs >= 0x0980 && ucs <= 0x09ff ) \
44 else if ( ucs >= 0x0a00 && ucs <= 0x0a7f ) \
46 else if ( ucs >= 0x0a80 && ucs <= 0x0aff ) \
48 else if ( ucs >= 0x0b00 && ucs <= 0x0b7f ) \
50 else if ( ucs >= 0x0b80 && ucs <= 0x0bff ) \
52 else if ( ucs >= 0x0c00 && ucs <= 0x0c7f ) \
54 else if ( ucs >= 0x0c80 && ucs <= 0x0cff ) \
56 else if ( ucs >= 0x0d00 && ucs <= 0x0d7f ) \
62 DEV, /* 0x42 */
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dphy_reg.h4 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
7 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
8 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
10 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
11 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
12 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
13 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
14 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
[all …]
H A Dclc_reg.h2 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
3 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
8 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
9 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
10 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
11 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
12 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
[all …]
/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Ddb21554_config.h39 #define DB_PCONF_PRI_HDR_OFF 0x00 /* primary offset on primary */
40 #define DB_PCONF_SEC_HDR_OFF 0x40 /* secondary offset on sec */
41 #define DB_SCONF_PRI_HDR_OFF 0x40 /* primary offset on sec */
42 #define DB_SCONF_SEC_HDR_OFF 0x00 /* secondary offset on sec */
43 #define DB_CONF_REGS 0x80 /* configuration regs after hdrs */
44 #define DB_SCONF_HDR_OFF 0x40 /* second config hdr offset */
70 #define DB_IO_BIT 0x00000001
74 #define DB_CONF_DS_CONF_ADDR 0x80 /* downstream config address */
75 #define DB_CONF_DS_CONF_DATA 0x84 /* downstream config data */
76 #define DB_CONF_US_CONF_ADDR 0x88 /* upstream config address */
[all …]
/illumos-gate/usr/src/uts/common/io/bnx/include/
H A Dlm_defs.h33 #define FALSE 0
37 #define NULL ((void *) 0)
42 #define LM_DEVICE_SIG 0x6d635242 /* BRcm */
43 #define L2PACKET_RX_SIG 0x7872324c /* L2rx */
44 #define L2PACKET_TX_SIG 0x7874324c /* L2tx */
45 #define L4BUFFER_RX_SIG 0x7872344c /* L4rx */
46 #define L4BUFFER_TX_SIG 0x7874344c /* L4tx */
47 #define L4BUFFER_SIG 0x66754254 /* TBuf */
48 #define L4GEN_BUFFER_SIG 0x006e6567 /* gen */
49 #define L4GEN_BUFFER_SIG_END 0x0067656e /* neg */
[all …]
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_phy_hw.h35 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved
48 #define BCM8704_CHIP_ID 0x8704
49 #define BCM8706_CHIP_ID 0x8706
50 #define MRVL88X201X_CHIP_ID 0x5043
51 #define NLP2020_CHIP_ID 0x0211
55 * The first nibble (bits 0 through 3) is changed with every revision
61 #define BCM_PHY_ID_MASK 0xfffff0f0
62 #define BCM8704_DEV_ID 0x206033
63 #define BCM5464R_PHY_ID 0x2060b1
64 #define BCM8706_DEV_ID 0x206035
[all …]
/illumos-gate/usr/src/data/locale/data/
H A Dkm_KH.UTF-8.src946 collating-symbol <X0B00>
1177 <X0B00>
1641 <KHMER_VOWEL_SIGN_OO-KHMER_SIGN_REAHMUK> "<X7797><X0B00>";<X05>;"<X05><XC0>";<KHMER_VOWEL_SIGN_OO-K…
1672 p_cs_precedes 0
1673 p_sep_by_space 0
1674 n_cs_precedes 0
1675 n_sep_by_space 0
1678 int_p_cs_precedes 0
1679 int_p_sep_by_space 0
1680 int_n_cs_precedes 0
[all …]
H A Dur_PK.UTF-8.src3845 collating-symbol <X0B00>
4190 <X0B00>
4741 … "<X651B><X0B00>";<X05>;"<X05><XC0…
5708 int_frac_digits 0
5709 frac_digits 0
/illumos-gate/usr/src/uts/common/io/i40e/core/
H A Di40e_adminq_cmd.h45 #define I40E_FW_API_VERSION_MAJOR 0x0001
46 #define I40E_FW_API_VERSION_MINOR_X722 0x000A
47 #define I40E_FW_API_VERSION_MINOR_X710 0x000A
54 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
56 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
58 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
60 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
87 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
92 #define I40E_AQ_FLAG_DD_SHIFT 0
104 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/include/
H A Dlm_defs.h50 #define FALSE 0
54 #define NULL ((void *) 0)
59 #define LM_DEVICE_SIG 0x6d635242 /* BRcm */
60 #define L2PACKET_RX_SIG 0x7872324c /* L2rx */
61 #define L2PACKET_TX_SIG 0x7874324c /* L2tx */
62 #define L4BUFFER_RX_SIG 0x7872344c /* L4rx */
63 #define L4BUFFER_TX_SIG 0x7874344c /* L4tx */
64 #define L4BUFFER_SIG 0x66754254 /* TBuf */
65 #define L4GEN_BUFFER_SIG 0x006e6567 /* gen */
66 #define L4GEN_BUFFER_SIG_END 0x0067656e /* neg */
[all …]
/illumos-gate/usr/src/uts/common/sys/scsi/adapters/pmcs/
H A Dpmcs_fwlog.h37 #define PMCS_SPREGS_BLOCK_START 0x0001
38 #define PMCS_SPREGS_BLOCK_END 0x0010
39 #define PMCS_SSPA_CONTROL_REGISTER_BIT27 0x01000000
52 {0x00030000, 0, 0x30C8, 0x30C8, PMCS_SPREGS_BLOCK_START, "HSST(A) - SM_CNTRL"},
53 {0x00030000, 0, 0x70C8, 0x70C8, 0, NULL},
54 {0x00030000, 0, 0xB0C8, 0xB0C8, 0, NULL},
55 {0x00030000, 0, 0xF0C8, 0xF0C8, 0, NULL},
56 {0x00040000, 0, 0x30C8, 0x30C8, 0, NULL},
57 {0x00040000, 0, 0x70C8, 0x70C8, 0, NULL},
58 {0x00040000, 0, 0xB0C8, 0xB0C8, 0, NULL},
[all …]
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dpci_ids.h9 #define PCI_CLASS_NOT_DEFINED 0x0000
10 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
12 #define PCI_BASE_CLASS_STORAGE 0x01
13 #define PCI_CLASS_STORAGE_SCSI 0x0100
14 #define PCI_CLASS_STORAGE_IDE 0x0101
15 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
16 #define PCI_CLASS_STORAGE_IPI 0x0103
17 #define PCI_CLASS_STORAGE_RAID 0x0104
18 #define PCI_CLASS_STORAGE_OTHER 0x0180
20 #define PCI_BASE_CLASS_NETWORK 0x02
[all …]
H A Dtulip.c58 support LNE100TX v2.0 cards, which use a different controller.
115 static int tulip_debug = 2; /* 1 normal messages, 0 quiet .. 7 verbose. */
135 #define TULIP_SIZE 0x80
141 #define FULL_DUPLEX_MAGIC 0x6969
143 static const int csr0 = 0x01A00000 | 0x8000;
157 DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
166 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
167 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
168 PCI_UNUSED_IRQ=0x800,
183 { "Digital DC21040 Tulip", { 0x00021011, 0xffffffff, 0, 0, 0, 0 },
[all …]
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_defines.h44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/illumos-gate/usr/src/uts/common/io/igc/core/
H A Digc_defines.h16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/illumos-gate/usr/src/uts/common/io/bge/
H A Dbge_hw.h56 #define VENDOR_ID_BROADCOM 0x14e4
57 #define VENDOR_ID_SUN 0x108e
59 #define DEVICE_ID_5700 0x1644
60 #define DEVICE_ID_5700x 0x0003
61 #define DEVICE_ID_5701 0x1645
62 #define DEVICE_ID_5702 0x16a6
63 #define DEVICE_ID_5702fe 0x164d
64 #define DEVICE_ID_5703C 0x16a7
65 #define DEVICE_ID_5703S 0x1647
66 #define DEVICE_ID_5703 0x16c7
[all …]
/illumos-gate/usr/src/common/bignum/sun4u/
H A Dmont_mulf_v8plus.s53 .word 0
61 .word 0
68 .word 0
69 .word 0
77 .word 0
85 .word 0
90 /* 000000 0 */ .align 4
157 ! 71 ! t1=0;
158 ! 72 ! a=(long long)d16[0];
160 /* 0x0004 72 */ ldd [%i1],%f0
[all …]
H A Dmont_mulf_v9.s39 .word 0
47 .word 0
54 .word 0
55 .word 0
63 .word 0
71 .word 0
76 /* 000000 0 */ .register %g3,#scratch
78 /* 000000 0 */ .align 8
80 /* 0x0018 */ .align 4
133 /* 0x0004 0 */ sethi %hi(Zero),%o3
[all …]
H A Dmont_mulf_kernel_v9.S66 .word 0
76 .word 0
85 .word 0
86 .word 0
96 .word 0
106 .word 0
111 /* 000000 0 */ .register %g3,#scratch
113 /* 000000 0 */ .align 32
165 /* 000000 57 */ sra %o1,0,%o4
166 /* 0x0004 */ sra %o2,0,%o5
[all …]
/illumos-gate/usr/src/uts/common/io/usb/
H A Dusbdevs54 * #define USB_VENDOR_VNDR 0x????
55 * #define USB_PRODUCT_VNDR_PRDCT 0x????
61 vendor UNKNOWN1 0x0053 Unknown vendor
62 vendor UNKNOWN2 0x0105 Unknown vendor
63 vendor EGALAX2 0x0123 eGalax, Inc.
64 vendor CHIPSBANK 0x0204 Chipsbank Microelectronics Co.
65 vendor HUMAX 0x02ad HUMAX
66 vendor QUAN 0x01e1 Quan
67 vendor LTS 0x0386 LTS
68 vendor BWCT 0x03da Bernd Walter Computer Technology
[all …]
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_type.h83 #define IXGBE_INTEL_VENDOR_ID 0x8086
86 #define IXGBE_DEV_ID_82598 0x10B6
87 #define IXGBE_DEV_ID_82598_BX 0x1508
88 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
89 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
90 #define IXGBE_DEV_ID_82598AT 0x10C8
91 #define IXGBE_DEV_ID_82598AT2 0x150B
92 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
93 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
94 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
[all …]
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_fw_2200.c51 unsigned short qlc_fw2200cs2_addr01 = 0x1000;
53 unsigned short risc_code_addr01 = 0x1000;
61 0x0470, 0x0000, 0x0000, 0xb604, 0x0000, 0x0002, 0x0001, 0x0091,
62 0x0037, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030,
63 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
64 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3232, 0x3030, 0x2046, 0x6972,
65 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
66 0x322e, 0x3031, 0x2e3e, 0x3520, 0x2020, 0x2020, 0x2400, 0x20c1,
67 0x0005, 0x20c9, 0xccff, 0x2091, 0x2000, 0x2059, 0x0000, 0x2b78,
68 0x7823, 0x0004, 0x2089, 0x2a39, 0x2051, 0xc700, 0x2a70, 0x2029,
[all …]
H A Dql_fw_2300.c51 unsigned short qlc_fw2300cs2_addr01 = 0x0800;
53 unsigned short risc_code_addr01 = 0x0800;
61 0x0470, 0x0000, 0x0000, 0xe8ee, 0x0000, 0x0003, 0x0003, 0x0079,
62 0x0037, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3031,
63 0x3520, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
64 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972,
65 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
66 0x332e, 0x3033, 0x2e3c, 0x3120, 0x2020, 0x2020, 0x2400, 0x20a9,
67 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f,
68 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001,
[all …]
H A Dql_fw_6322.c51 unsigned short qlc_fw2300flcs2_addr01 = 0x0800;
53 unsigned short risc_code_addr01 = 0x0800;
61 0x0470, 0x0000, 0x0000, 0xd658, 0x0000, 0x0003, 0x0003, 0x001c,
62 0x0217, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030,
63 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241,
64 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972,
65 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030,
66 0x332e, 0x3033, 0x2e32, 0x3820, 0x2020, 0x2020, 0x2400, 0x20a9,
67 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f,
68 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001,
[all …]

12