Home
last modified time | relevance | path

Searched +full:0 +full:x0a00 (Results 1 – 25 of 152) sorted by relevance

1234567

/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-exynos5433.c50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
[all …]
/linux/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dgate.txt31 - #clock-cells : from common clock binding; shall be set to 0
45 #clock-cells = <0>;
48 reg = <0x0a00>;
53 #clock-cells = <0>;
56 reg = <0x0a00>;
61 #clock-cells = <0>;
64 reg = <0x0e00>;
65 ti,bit-shift = <0>;
69 #clock-cells = <0>;
72 reg = <0x059c>;
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/linux/drivers/media/i2c/
H A Dhi556.c26 #define HI556_REG_CHIP_ID 0x0f16
27 #define HI556_CHIP_ID 0x0556
29 #define HI556_REG_MODE_SELECT 0x0a00
30 #define HI556_MODE_STANDBY 0x0000
31 #define HI556_MODE_STREAMING 0x0100
34 #define HI556_REG_FLL 0x0006
35 #define HI556_FLL_30FPS 0x0814
36 #define HI556_FLL_30FPS_MIN 0x0814
37 #define HI556_FLL_MAX 0x7fff
40 #define HI556_REG_LLP 0x0008
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
H A Dprcm-common.h22 #define OCP_MOD 0x000
23 #define MPU_MOD 0x100
24 #define CORE_MOD 0x200
25 #define GFX_MOD 0x300
26 #define WKUP_MOD 0x400
27 #define PLL_MOD 0x500
32 #define OMAP24XX_DSP_MOD 0x800
34 #define OMAP2430_MDM_MOD 0xc00
37 #define OMAP3430_IVA2_MOD -0x800
40 #define OMAP3430_DSS_MOD 0x600
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.c13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c14 /* 0x27200000 + 0x0A00 */
15 #define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0x27208000 + 0x0A00 */
17 #define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
18 /* 0x27210000 + 0x0A00 */
19 #define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
20 /* 0x27220000 + 0x0A00 */
21 #define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
33 RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
55 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
[all …]
H A Drst-rk3588.c13 /* 0xFD7C0000 + 0x0A00 */
14 #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0xFD7C8000 + 0x0A00 */
17 #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
19 /* 0xFD7D0000 + 0x0A00 */
20 #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
22 /* 0xFD7F0000 + 0x0A00 */
23 #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
37 RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
48 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
[all …]
/linux/drivers/net/phy/
H A Dmdio-open-alliance.h14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm281xx.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .trig = TRIGGER(0x0e04, 0),
18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .sel = SELECTOR(0x0a04, 0, 2),
48 .div = DIVIDER(0x0a04, 3, 4),
49 .trig = TRIGGER(0x0a40, 0),
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-technisat-usb2.c32 {0x0a0c, KEY_POWER},
33 {0x0a01, KEY_NUMERIC_1},
34 {0x0a02, KEY_NUMERIC_2},
35 {0x0a03, KEY_NUMERIC_3},
36 {0x0a0d, KEY_MUTE},
37 {0x0a04, KEY_NUMERIC_4},
38 {0x0a05, KEY_NUMERIC_5},
39 {0x0a06, KEY_NUMERIC_6},
40 {0x0a38, KEY_VIDEO}, /* EXT */
41 {0x0a07, KEY_NUMERIC_7},
[all …]
/linux/sound/soc/codecs/
H A Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/linux/arch/m68k/include/asm/
H A Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux/sound/pci/cs46xx/
H A Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]

1234567