Home
last modified time | relevance | path

Searched +full:0 +full:x09c (Results 1 – 25 of 69) sorted by relevance

123

/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dwcs.h33 0x011, // 00000 = 0 - PHY_RESET_START
34 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY
35 0x009, // 0x002 = 2 -
36 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE
37 0x010, // 0x004 = 4 -
38 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED
39 0x01e, // 0x006 = 6 -
40 0x0ff, // 0x007 = 7 - JUMP
41 0x001, // 0x008 = 8 -
42 0x010, // 0x009 = 9 - SEND_ID_FRAME
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-sdp-es23plus.dts10 OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
11 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
12 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
H A Domap4-panda-a4.dts18 OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
19 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
20 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
H A Domap4-panda-es.dts34 OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
35 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
36 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
43 OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
49 OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
56 OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
61 pinctrl-0 = <
H A Domap4-duovero-parlor.dts31 #size-cells = <0>;
59 pinctrl-0 = <
67 OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */
73 OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */
79 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
80 OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
86 OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
87 OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
93 OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */
94 OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */
[all …]
H A Domap4-var-om44customboard.dtsi16 pinctrl-0 = <&gpio_led_pins>;
33 pinctrl-0 = <&gpio_key_pins>;
35 #size-cells = <0>;
48 pinctrl-0 = <&hdmi_hpd_pins>;
65 OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */
66 OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */
67 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */
68 OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */
74 OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
75 OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sa8775p-mdss.yaml38 "^display-controller@[0-9a-f]+$":
46 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
90 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x1000 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
141 interrupts = <0>;
145 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq6h-pins.dtsi9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
27 0x000 0x200 // I2C0_SCL pin
28 0x004 0x200 // I2C0_SDA pin
33 0x008 0x200 // I2C1_SCL pin
34 0x00c 0x200 // I2C1_SDA pin
39 0x080 1 // GPIO_C4__SMA0_MDC pin
40 0x084 1 // GPIO_C5__SMA0_MDIO pin
44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721s2-evm-gesi-exp-board.dtso27 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
28 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
34 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
35 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
36 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
37 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
38 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
39 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
40 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
41 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
[all …]
H A Dk3-am68-phycore-som.dtsi28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
29 <0x00000008 0x80000000 0x00000000 0x80000000>;
42 size = <0x00 0x20000000>;
47 reg = <0x00 0x9e800000 0x00 0x01800000>;
48 alignment = <0x1000>;
54 reg = <0x00 0xa0000000 0x00 0x100000>;
60 reg = <0x00 0xa0100000 0x00 0xf00000>;
66 reg = <0x00 0xa1000000 0x00 0x100000>;
72 reg = <0x00 0xa1100000 0x00 0xf00000>;
78 reg = <0x00 0xa2000000 0x00 0x100000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h37 #define MT_HW_REV MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h31 #define AR40XX_PORT_LINK_DOWN 0
33 #define AR40XX_QM_EMPTY 0
39 PORT_WRAPPER_PSGMII = 0,
48 #define AR40XX_PORT_CPU 0
50 #define AR40XX_PSGMII_MODE_CONTROL 0x1b4
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
53 #define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
55 #define AR40XX_MII_ATH_MMD_ADDR 0x0d
56 #define AR40XX_MII_ATH_MMD_DATA 0x0e
57 #define AR40XX_MII_ATH_DBG_ADDR 0x1d
[all …]
/freebsd/sys/dev/nfe/
H A Dif_nfereg.h45 #define NFE_IRQ_STATUS 0x000
46 #define NFE_IRQ_MASK 0x004
47 #define NFE_SETUP_R6 0x008
48 #define NFE_IMTIMER 0x00c
49 #define NFE_MSI_MAP0 0x020
50 #define NFE_MSI_MAP1 0x024
51 #define NFE_MSI_IRQ_MASK 0x030
52 #define NFE_MAC_RESET 0x03c
53 #define NFE_MISC1 0x080
54 #define NFE_TX_CTL 0x084
[all …]

123