1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Dominik Haller <d.haller@phytec.de> 5 * 6 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-j721s2.dtsi" 14 15/ { 16 compatible = "phytec,am68-phycore-som", "ti,j721s2"; 17 model = "PHYTEC phyCORE-AM68x"; 18 19 aliases { 20 ethernet1 = &main_cpsw_port1; 21 mmc0 = &main_sdhci0; 22 rtc0 = &i2c_som_rtc; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 /* 4GB RAM */ 28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 29 <0x00000008 0x80000000 0x00000000 0x80000000>; 30 bootph-all; 31 }; 32 33 reserved_memory: reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 /* global cma region */ 39 linux,cma { 40 compatible = "shared-dma-pool"; 41 reusable; 42 size = <0x00 0x20000000>; 43 linux,cma-default; 44 }; 45 46 secure_ddr: optee@9e800000 { 47 reg = <0x00 0x9e800000 0x00 0x01800000>; 48 alignment = <0x1000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1000000 0x00 0x100000>; 67 no-map; 68 }; 69 70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa1100000 0x00 0xf00000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2000000 0x00 0x100000>; 79 no-map; 80 }; 81 82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa2100000 0x00 0xf00000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3000000 0x00 0x100000>; 91 no-map; 92 }; 93 94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa3100000 0x00 0xf00000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4000000 0x00 0x100000>; 103 no-map; 104 }; 105 106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa4100000 0x00 0xf00000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5000000 0x00 0x100000>; 115 no-map; 116 }; 117 118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa5100000 0x00 0xf00000>; 121 no-map; 122 }; 123 124 c71_0_dma_memory_region: c71-dma-memory@a6000000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6000000 0x00 0x100000>; 127 no-map; 128 }; 129 130 c71_0_memory_region: c71-memory@a6100000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa6100000 0x00 0xf00000>; 133 no-map; 134 }; 135 136 c71_1_dma_memory_region: c71-dma-memory@a7000000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7000000 0x00 0x100000>; 139 no-map; 140 }; 141 142 c71_1_memory_region: c71-memory@a7100000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa7100000 0x00 0xf00000>; 145 no-map; 146 }; 147 148 rtos_ipc_memory_region: ipc-memories@a8000000 { 149 reg = <0x00 0xa8000000 0x00 0x01c00000>; 150 alignment = <0x1000>; 151 no-map; 152 }; 153 }; 154 155 vdd_sd_dv: regulator-sd { 156 /* Output of TLV71033 */ 157 compatible = "regulator-gpio"; 158 regulator-name = "VDD_SD_DV"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&vdd_sd_dv_pins_default>; 161 regulator-min-microvolt = <1800000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 gpios = <&main_gpio0 1 GPIO_ACTIVE_HIGH>; 165 states = <3300000 0x0>, 166 <1800000 0x1>; 167 }; 168}; 169 170&main_pmx0 { 171 main_cpsw_mdio_pins_default: main-cpsw-mdio-default-pins { 172 pinctrl-single,pins = < 173 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ 174 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ 175 >; 176 }; 177 178 main_i2c0_pins_default: main-i2c0-default-pins { 179 pinctrl-single,pins = < 180 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ 181 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ 182 >; 183 }; 184 185 rgmii1_pins_default: rgmii1-default-pins { 186 pinctrl-single,pins = < 187 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ 188 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ 189 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ 190 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ 191 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ 192 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ 193 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ 194 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ 195 J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ 196 J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ 197 J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ 198 J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ 199 >; 200 }; 201 202 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 203 pinctrl-single,pins = < 204 J721S2_IOPAD(0x004, PIN_OUTPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ 205 >; 206 }; 207}; 208 209&wkup_pmx0 { 210 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 211 pinctrl-single,pins = < 212 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 213 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 214 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 215 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 216 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 217 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 218 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 219 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 220 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 221 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 222 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 223 >; 224 bootph-all; 225 }; 226}; 227 228&wkup_pmx1 { 229 pmic_irq_pins_default: pmic-irq-default-pins { 230 pinctrl-single,pins = < 231 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 232 >; 233 }; 234}; 235 236&wkup_pmx2 { 237 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 238 pinctrl-single,pins = < 239 J721S2_WKUP_IOPAD(0x098, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SCL */ 240 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ 241 >; 242 bootph-all; 243 }; 244}; 245 246&c71_0 { 247 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 248 memory-region = <&c71_0_dma_memory_region>, 249 <&c71_0_memory_region>; 250 status = "okay"; 251}; 252 253&c71_1 { 254 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 255 memory-region = <&c71_1_dma_memory_region>, 256 <&c71_1_memory_region>; 257 status = "okay"; 258}; 259 260&mailbox0_cluster0 { 261 interrupts = <436>; 262 status = "okay"; 263 264 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 265 ti,mbox-rx = <0 0 0>; 266 ti,mbox-tx = <1 0 0>; 267 }; 268 269 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 270 ti,mbox-rx = <2 0 0>; 271 ti,mbox-tx = <3 0 0>; 272 }; 273}; 274 275&mailbox0_cluster1 { 276 interrupts = <432>; 277 status = "okay"; 278 279 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 280 ti,mbox-rx = <0 0 0>; 281 ti,mbox-tx = <1 0 0>; 282 }; 283 284 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 285 ti,mbox-rx = <2 0 0>; 286 ti,mbox-tx = <3 0 0>; 287 }; 288}; 289 290&mailbox0_cluster2 { 291 interrupts = <428>; 292 status = "okay"; 293 294 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 295 ti,mbox-rx = <0 0 0>; 296 ti,mbox-tx = <1 0 0>; 297 }; 298 299 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 300 ti,mbox-rx = <2 0 0>; 301 ti,mbox-tx = <3 0 0>; 302 }; 303}; 304 305&mailbox0_cluster4 { 306 interrupts = <420>; 307 status = "okay"; 308 309 mbox_c71_0: mbox-c71-0 { 310 ti,mbox-rx = <0 0 0>; 311 ti,mbox-tx = <1 0 0>; 312 }; 313 314 mbox_c71_1: mbox-c71-1 { 315 ti,mbox-rx = <2 0 0>; 316 ti,mbox-tx = <3 0 0>; 317 }; 318}; 319 320&main_cpsw { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&rgmii1_pins_default>; 323 status = "okay"; 324}; 325 326&main_cpsw_mdio { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&main_cpsw_mdio_pins_default>; 329 status = "okay"; 330 331 phy1: ethernet-phy@0 { 332 reg = <0>; 333 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 334 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 335 ti,min-output-impedance; 336 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 337 }; 338}; 339 340&main_cpsw_port1 { 341 phy-handle = <&phy1>; 342 phy-mode = "rgmii-rxid"; 343 status = "okay"; 344}; 345 346&main_i2c0 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&main_i2c0_pins_default>; 349 350 temperature-sensor@48 { 351 compatible = "ti,tmp102"; 352 reg = <0x48>; 353 }; 354 355 temperature-sensor@49 { 356 compatible = "ti,tmp102"; 357 reg = <0x49>; 358 }; 359 360 i2c_som_rtc: rtc@52 { 361 compatible = "microcrystal,rv3028"; 362 reg = <0x52>; 363 }; 364}; 365 366&main_gpio0 { 367 status = "okay"; 368}; 369 370&main_r5fss0_core0 { 371 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 372 memory-region = <&main_r5fss0_core0_dma_memory_region>, 373 <&main_r5fss0_core0_memory_region>; 374}; 375 376&main_r5fss0_core1 { 377 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 378 memory-region = <&main_r5fss0_core1_dma_memory_region>, 379 <&main_r5fss0_core1_memory_region>; 380}; 381 382&main_r5fss1_core0 { 383 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 384 memory-region = <&main_r5fss1_core0_dma_memory_region>, 385 <&main_r5fss1_core0_memory_region>; 386}; 387 388&main_r5fss1_core1 { 389 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 390 memory-region = <&main_r5fss1_core1_dma_memory_region>, 391 <&main_r5fss1_core1_memory_region>; 392}; 393 394/* eMMC */ 395&main_sdhci0 { 396 non-removable; 397 ti,driver-strength-ohm = <50>; 398 bootph-all; 399 status = "okay"; 400}; 401 402/* SD card */ 403&main_sdhci1 { 404 vqmmc-supply = <&vdd_sd_dv>; 405 bootph-all; 406}; 407 408&main_r5fss0 { 409 ti,cluster-mode = <0>; 410}; 411 412&main_r5fss1 { 413 ti,cluster-mode = <0>; 414}; 415 416/* Timers are used by Remoteproc firmware */ 417&main_timer0 { 418 status = "reserved"; 419}; 420 421&main_timer1 { 422 status = "reserved"; 423}; 424 425&main_timer2 { 426 status = "reserved"; 427}; 428 429&main_timer3 { 430 status = "reserved"; 431}; 432 433&main_timer4 { 434 status = "reserved"; 435}; 436 437&main_timer5 { 438 status = "reserved"; 439}; 440 441&mcu_r5fss0_core0 { 442 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 443 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 444 <&mcu_r5fss0_core0_memory_region>; 445}; 446 447&mcu_r5fss0_core1 { 448 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 449 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 450 <&mcu_r5fss0_core1_memory_region>; 451}; 452 453&ospi0 { 454 pinctrl-names = "default"; 455 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 456 status = "okay"; 457 458 serial_flash: flash@0 { 459 compatible = "jedec,spi-nor"; 460 reg = <0x0>; 461 spi-tx-bus-width = <8>; 462 spi-rx-bus-width = <8>; 463 spi-max-frequency = <25000000>; 464 cdns,tshsl-ns = <60>; 465 cdns,tsd2d-ns = <60>; 466 cdns,tchsh-ns = <60>; 467 cdns,tslch-ns = <60>; 468 cdns,read-delay = <2>; 469 bootph-all; 470 }; 471}; 472 473&wkup_gpio0 { 474 status = "okay"; 475}; 476 477&wkup_i2c0 { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&wkup_i2c0_pins_default>; 480 clock-frequency = <400000>; 481 status = "okay"; 482 483 vdd_cpu_avs: regulator@40 { 484 compatible = "ti,tps62873"; 485 reg = <0x40>; 486 regulator-name = "VDD_CPU_AVS"; 487 regulator-min-microvolt = <600000>; 488 regulator-max-microvolt = <900000>; 489 regulator-boot-on; 490 regulator-always-on; 491 bootph-pre-ram; 492 }; 493 494 pmic@48 { 495 compatible = "ti,tps6594-q1"; 496 reg = <0x48>; 497 system-power-controller; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pmic_irq_pins_default>; 500 interrupt-parent = <&wkup_gpio0>; 501 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 buck12-supply = <&vcc_3v3>; 505 buck3-supply = <&vcc_3v3>; 506 buck4-supply = <&vcc_3v3>; 507 buck5-supply = <&vcc_3v3>; 508 ldo1-supply = <&vcc_3v3>; 509 ldo2-supply = <&vcc_3v3>; 510 ldo3-supply = <&vcc_3v3>; 511 ldo4-supply = <&vcc_3v3>; 512 ti,primary-pmic; 513 514 regulators { 515 bucka12: buck12 { 516 regulator-name = "VDD_DDR_1V1"; 517 regulator-min-microvolt = <1100000>; 518 regulator-max-microvolt = <1100000>; 519 regulator-boot-on; 520 regulator-always-on; 521 bootph-all; 522 }; 523 524 bucka3: buck3 { 525 regulator-name = "VDD_RAM_0V85"; 526 regulator-min-microvolt = <850000>; 527 regulator-max-microvolt = <850000>; 528 regulator-boot-on; 529 regulator-always-on; 530 bootph-all; 531 }; 532 533 bucka4: buck4 { 534 regulator-name = "VDD_IO_1V8"; 535 regulator-min-microvolt = <1800000>; 536 regulator-max-microvolt = <1800000>; 537 regulator-boot-on; 538 regulator-always-on; 539 bootph-all; 540 }; 541 542 bucka5: buck5 { 543 regulator-name = "VDD_MCU_0V85"; 544 regulator-min-microvolt = <850000>; 545 regulator-max-microvolt = <850000>; 546 regulator-boot-on; 547 regulator-always-on; 548 bootph-all; 549 }; 550 551 ldoa1: ldo1 { 552 regulator-name = "VDD_MCUIO_1V8"; 553 regulator-min-microvolt = <1800000>; 554 regulator-max-microvolt = <1800000>; 555 regulator-boot-on; 556 regulator-always-on; 557 bootph-all; 558 }; 559 560 ldoa2: ldo2 { 561 regulator-name = "VDD_MCUIO_3V3"; 562 regulator-min-microvolt = <3300000>; 563 regulator-max-microvolt = <3300000>; 564 regulator-boot-on; 565 regulator-always-on; 566 bootph-all; 567 }; 568 569 ldoa3: ldo3 { 570 regulator-name = "VDDA_DLL_0V8"; 571 regulator-min-microvolt = <800000>; 572 regulator-max-microvolt = <800000>; 573 regulator-boot-on; 574 regulator-always-on; 575 bootph-all; 576 }; 577 578 ldoa4: ldo4 { 579 regulator-name = "VDDA_MCU_1V8"; 580 regulator-min-microvolt = <1800000>; 581 regulator-max-microvolt = <1800000>; 582 regulator-boot-on; 583 regulator-always-on; 584 bootph-all; 585 }; 586 }; 587 }; 588 589 eeprom@50 { 590 compatible = "atmel,24c32"; 591 reg = <0x50>; 592 pagesize = <32>; 593 bootph-all; 594 }; 595 596 som_eeprom_opt: eeprom@51 { 597 compatible = "atmel,24c32"; 598 reg = <0x51>; 599 pagesize = <32>; 600 }; 601}; 602