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/linux/drivers/scsi/megaraid/
H A Dmegaraid_mbox.h27 #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E
28 #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123
30 #define PCI_DEVICE_ID_PERC4_SC 0x1960
31 #define PCI_SUBSYS_ID_PERC4_SC 0x0520
33 #define PCI_DEVICE_ID_PERC4_DC 0x1960
34 #define PCI_SUBSYS_ID_PERC4_DC 0x0518
36 #define PCI_DEVICE_ID_VERDE 0x0407
38 #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
39 #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
41 #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,apll-clock.yaml30 const: 0
71 #size-cells = <0>;
74 #clock-cells = <0>;
77 reg = <0x021c>, <0x0220>;
81 #clock-cells = <0>;
87 reg = <0x0500>, <0x0530>, <0x0520>;
/linux/drivers/net/dsa/microchip/
H A Dksz_ptp_reg.h9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
25 #define PTP_CLK_RESET BIT(0)
28 #define PTP_RTC_SUB_NANOSEC_M 0x0007
29 #define PTP_RTC_0NS 0x00
32 #define PTP_SUBNANOSEC_M 0x3FFFFFFF
36 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E
38 #define REG_PTP_RATE_DURATION 0x0510
39 #define REG_PTP_RATE_DURATION_H 0x0510
[all …]
/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_regs.h13 #define MLXBF_GIGE_VERSION 0x0000
14 #define MLXBF_GIGE_VERSION_BF2 0x0
15 #define MLXBF_GIGE_VERSION_BF3 0x1
16 #define MLXBF_GIGE_STATUS 0x0010
17 #define MLXBF_GIGE_STATUS_READY BIT(0)
18 #define MLXBF_GIGE_INT_STATUS 0x0028
19 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)
28 #define MLXBF_GIGE_INT_EN 0x0030
29 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)
38 #define MLXBF_GIGE_INT_MASK 0x0038
[all …]
/linux/include/linux/usb/
H A Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
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/linux/drivers/clk/mediatek/
H A Dclk-mt8188-apmixedsys.c15 .set_ofs = 0x8,
16 .clr_ofs = 0x8,
17 .sta_ofs = 0x8,
60 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
61 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
62 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
63 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
64 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
65 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
66 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-hpa-regs.h20 #define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000
21 #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00
22 #define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000
25 #define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000
26 #define CDNS_PCIE_HPA_AXI_MASTER 0x03002000
29 #define CDNS_PCIE_HPA_RP_BASE 0x0
31 #define CDNS_PCIE_HPA_LM_ID 0x1420
37 #define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn))
38 #define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04)
42 #define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08)
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/linux/drivers/gpu/drm/exynos/
H A Dregs-decon5433.h10 #define DECON_VIDCON0 0x0000
11 #define DECON_VIDOUTCON0 0x0010
12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4))
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
14 #define DECON_SHADOWCON 0x00A0
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
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H A Dregs-hdmi.h20 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
21 #define HDMI_CORE_BASE(x) ((x) + 0x00010000)
22 #define HDMI_I2S_BASE(x) ((x) + 0x00040000)
23 #define HDMI_TG_BASE(x) ((x) + 0x00050000)
26 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
27 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
28 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
29 #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
30 #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)
31 #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)
[all …]
/linux/include/linux/mfd/mt6323/
H A Dregisters.h10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgk104.c37 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_vsi()
42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000); in gk104_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x690108 + hoff, vsi.header); in gk104_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x69010c + hoff, vsi.subpack0_low); in gk104_sor_hdmi_infoframe_vsi()
48 nvkm_wr32(device, 0x690110 + hoff, vsi.subpack0_high); in gk104_sor_hdmi_infoframe_vsi()
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_vsi()
58 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_avi()
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000); in gk104_sor_hdmi_infoframe_avi()
67 nvkm_wr32(device, 0x690008 + hoff, avi.header); in gk104_sor_hdmi_infoframe_avi()
68 nvkm_wr32(device, 0x69000c + hoff, avi.subpack0_low); in gk104_sor_hdmi_infoframe_avi()
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h6 #define PA_NORFLASH_ADDR 0x00000000
7 #define PA_NORFLASH_SIZE 0x04000000
10 #define PA_BCR 0xa4000000 /* FPGA */
13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
16 #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
17 #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
18 #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
[all …]
/linux/sound/soc/codecs/
H A Drt700-sdw.h12 { 0x0000, 0x0000 },
13 { 0x0001, 0x0000 },
14 { 0x0002, 0x0000 },
15 { 0x0003, 0x0000 },
16 { 0x0004, 0x000
[all...]
H A Drt1011.h11 #define RT1011_DEVICE_ID_NUM 0x1011
13 #define RT1011_RESET 0x0000
14 #define RT1011_CLK_1 0x0002
15 #define RT1011_CLK_2 0x0004
16 #define RT1011_CLK_3 0x0006
17 #define RT1011_CLK_4 0x0008
18 #define RT1011_PLL_1 0x000a
19 #define RT1011_PLL_2 0x000c
20 #define RT1011_SRC_1 0x000e
21 #define RT1011_SRC_2 0x0010
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x4>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x4>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/include/linux/
H A Dpe.h14 * Starting from version v3.0, the major version field should be interpreted as
16 * - 0x1: initrd loading from the LINUX_EFI_INITRD_MEDIA_GUID device path,
17 * - 0x2: initrd loading using the initrd= command line option, where the file
21 * The recommended way of loading and starting v1.0 or later kernels is to use
25 * Versions older than v1.0 may support initrd loading via the image load
29 * The minor version field must remain 0x0.
32 #define LINUX_EFISTUB_MAJOR_VERSION 0x3
33 #define LINUX_EFISTUB_MINOR_VERSION 0x0
36 * LINUX_PE_MAGIC appears at offset 0x38 into the MS-DOS header of EFI bootable
40 #define LINUX_PE_MAGIC 0x818223cd
[all …]

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