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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/linux/arch/s390/include/asm/
H A Dlowcore.h22 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
31 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
32 __u32 ipl_parmblock_ptr; /* 0x0014 */
33 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
34 __u32 ext_params; /* 0x0080 */
37 __u16 ext_cpu_addr; /* 0x0084 */
38 __u16 ext_int_code; /* 0x0086 */
42 __u32 svc_int_code; /* 0x0088 */
45 __u16 pgm_ilc; /* 0x008c */
46 __u16 pgm_code; /* 0x008e */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7d-pinctrl.yaml94 reg = <0x30330000 0x10000>;
98 <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
99 <0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
105 reg = <0x302c0000 0x10000>;
110 <0x0008 0x0038 0x0000 0x0 0x0 0x59>,
111 <0x000C 0x003C 0x0000 0x0 0x0 0x59>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_0_offset.h28 // base address: 0x0
29 …MP1_SMN_C2PMSG_0 0x0240
30 …e regMP1_SMN_C2PMSG_0_BASE_IDX 0
31 …MP1_SMN_C2PMSG_1 0x0241
32 …e regMP1_SMN_C2PMSG_1_BASE_IDX 0
33 …MP1_SMN_C2PMSG_2 0x0242
34 …e regMP1_SMN_C2PMSG_2_BASE_IDX 0
35 …MP1_SMN_C2PMSG_3 0x0243
36 …e regMP1_SMN_C2PMSG_3_BASE_IDX 0
37 …MP1_SMN_C2PMSG_4 0x0244
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-rpgate.c17 #define R_SYSGATE_BEGIN 0x0368
18 #define R_RP_RXU_CLK_ENABLE (0x0368 - R_SYSGATE_BEGIN)
19 #define R_MP0_STATUS_REG (0x0380 - R_SYSGATE_BEGIN)
20 #define R_MP0_CONTROL_REG (0x0384 - R_SYSGATE_BEGIN)
21 #define R_MP1_STATUS_REG (0x0388 - R_SYSGATE_BEGIN)
22 #define R_MP1_CONTROL_REG (0x038C - R_SYSGATE_BEGIN)
23 #define R_MP2_STATUS_REG (0x0390 - R_SYSGATE_BEGIN)
24 #define R_MP2_CONTROL_REG (0x0394 - R_SYSGATE_BEGIN)
25 #define R_MP3_STATUS_REG (0x0398 - R_SYSGATE_BEGIN)
26 #define R_MP3_CONTROL_REG (0x039C - R_SYSGATE_BEGIN)
[all …]
/linux/include/linux/usb/
H A Dnet2280.h24 /* main registers, BAR0 + 0x0000 */
26 /* offset 0x0000 */
36 #define M8051_RESET 0
47 #define EEPROM_WRITE_DATA 0
50 /* offset 0x0010 */
60 #define ENDPOINT_0_INTERRUPT_ENABLE 0
83 #define SOF_INTERRUPT_ENABLE 0
92 #define ENDPOINT_0_INTERRUPT_ENABLE 0
118 #define SOF_INTERRUPT_ENABLE 0
120 /* offset 0x0020 */
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c74 found = 0; in nv04_calc_arb()
95 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
149 mclks += (arb->memory_type == 0 ? 2 : 1) in nv10_calc_arb()
210 if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ || in nv04_update_arb()
211 (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) { in nv04_update_arb()
215 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1), in nv04_update_arb()
216 0x7c, &type); in nv04_update_arb()
223 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; in nv04_update_arb()
224 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
225 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
H A Drswitch.h18 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
24 for (; i-- > 0; ) \
45 #define RSWITCH_TOP_OFFSET 0x00008000
46 #define RSWITCH_COMA_OFFSET 0x00009000
47 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
48 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
49 #define RSWITCH_GWCA0_OFFSET 0x00010000
50 #define RSWITCH_GWCA1_OFFSET 0x00012000
56 #define GWCA_INDEX 0
58 #define GWCA_IPV_NUM 0
[all …]
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dvpdma_priv.h18 #define VPDMA_PID 0x00
19 #define VPDMA_LIST_ADDR 0x04
20 #define VPDMA_LIST_ATTR 0x08
21 #define VPDMA_LIST_STAT_SYNC 0x0c
22 #define VPDMA_BG_RGB 0x18
23 #define VPDMA_BG_YUV 0x1c
24 #define VPDMA_SETUP 0x30
25 #define VPDMA_MAX_SIZE1 0x34
26 #define VPDMA_MAX_SIZE2 0x38
27 #define VPDMA_MAX_SIZE3 0x3c
[all …]
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
67 cr11 |= 0x80; in NVLockUnlock()
69 cr11 &= ~0x80; in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
78 (ShowHide & 0x01); in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h26 #define CN6XXX_XPANSION_BAR 0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux/include/video/
H A Dmach64.h20 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21 #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23 #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
24 #define CRTC_H_SYNC_STRT 0x0004
25 #define CRTC2_H_SYNC_STRT 0x0004
26 #define CRTC_H_SYNC_DLY 0x0005
27 #define CRTC2_H_SYNC_DLY 0x0005
28 #define CRTC_H_SYNC_WID 0x0006
29 #define CRTC2_H_SYNC_WID 0x0006
[all …]
/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/sound/soc/codecs/
H A Drt5663.h15 #define RT5663_RESET 0x0000
16 #define RT5663_VENDOR_ID 0x00fd
17 #define RT5663_VENDOR_ID_1 0x00fe
18 #define RT5663_VENDOR_ID_2 0x00ff
20 #define RT5663_LOUT_CTRL 0x0001
21 #define RT5663_HP_AMP_2 0x0003
22 #define RT5663_MONO_OUT 0x0004
23 #define RT5663_MONO_GAIN 0x0007
25 #define RT5663_AEC_BST 0x000b
26 #define RT5663_IN1_IN2 0x000c
[all …]

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