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/linux/arch/loongarch/include/asm/
H A Dalternative-asm.h33 .fill - (((144f-143f)-(141b-140b)) > 0) * ((144f-143f)-(141b-140b)) / 4, 4, 0x03400000
62 .fill - ((alt_max_short(new_len1, new_len2) - (old_len)) > 0) * \
63 (alt_max_short(new_len1, new_len2) - (old_len)) / 4, 4, 0x03400000
H A Dalternative.h40 ".fill -(((" alt_rlen(num) ")-(" alt_slen ")) > 0) * " \
41 "((" alt_rlen(num) ")-(" alt_slen ")) / 4, 4, 0x03400000\n"
55 ".fill -((" alt_max_short(alt_rlen(num1), alt_rlen(num2)) " - (" alt_slen ")) > 0) * " \
57 "4, 0x03400000\n" \
H A Dinst.h13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
15 #define INSN_HVCL 0x002b8000
17 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
18 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
19 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
20 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
21 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
29 #define ADDR_IMMSHIFT_ORI 0
38 break_op = 0x54,
[all …]
/linux/tools/arch/loongarch/include/asm/
H A Dinst.h10 #define LOONGARCH_INSN_NOP 0x03400000
13 break_op = 0x54,
17 b_op = 0x14,
18 bl_op = 0x15,
22 beqz_op = 0x10,
23 bnez_op = 0x11,
24 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
25 bcnez_op = 0x1
[all...]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sdm670-tlmm.yaml57 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
99 reg = <0x03400000 0x300000>;
105 gpio-ranges = <&tlmm 0 0 151>;
H A Dqcom,sdm845-pinctrl.yaml45 "-hog(-[0-9]+)?$":
66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
115 reg = <0x03400000 0xc00000>;
121 gpio-ranges = <&tlmm 0 0 151>;
H A Dqcom,msm8998-pinctrl.yaml58 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
122 reg = <0x03400000 0xc00000>;
124 gpio-ranges = <&tlmm 0 0 150>;
129 gpio-reserved-ranges = <0 4>, <81 4>;
/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,layerscape-pcie.yaml50 physical PCIe controller index starting from '0'. This is used to get
55 - description: PCIe controller index starting from '0'
160 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
161 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
163 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
169 bus-range = <0x0 0xff>;
170 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
171 … 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
174 interrupt-map-mask = <0 0 0 7>;
175 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a.dtsi23 cpu0: cpu@0 {
26 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
36 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
46 reg = <0x100>;
56 reg = <0x101>;
66 reg = <0x200>;
76 reg = <0x201>;
86 reg = <0x300>;
[all …]
H A Dfsl-ls2080a.dtsi23 cpu0: cpu@0 {
26 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
36 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
46 reg = <0x100>;
56 reg = <0x101>;
66 reg = <0x200>;
76 reg = <0x201>;
86 reg = <0x300>;
[all …]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/linux/arch/arm/mach-rpc/
H A Driscpc.c56 #if 0 in parse_tag_acorn()
58 desc->video_start = 0x02000000; in parse_tag_acorn()
59 desc->video_end = 0x02000000 + vram_size; in parse_tag_acorn()
62 return 0; in parse_tag_acorn()
93 writeb(0xc, PCIO_BASE + (0x3f2 << 2)); in rpc_map_io()
103 DEFINE_RES_MEM(0x03400000, 0x00200000),
111 .coherent_dma_mask = 0xffffffff,
118 DEFINE_RES_MEM(0x03200000, 0x10000),
145 .mapbase = 0x03010fe0,
168 DEFINE_RES_MEM(0x030107c0, 0x20),
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992-lg-h815.dts26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
39 reg = <0x0 0x06000000 0x0 0x00001000>;
45 reg = <0x0 0x0ff00000 0x0 0x00100000>;
46 console-size = <0x20000>;
47 pmsg-size = <0x20000>;
48 record-size = <0x10000>;
49 ecc-size = <0x10>;
53 reg = <0x0 0x03400000 0x0 0x00c00000>;
[all …]
H A Dmsm8992-lg-bullhead.dtsi26 qcom,msm-id = <251 0>, <252 0>;
27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
47 reg = <0x0 0x1ff00000 0x0 0x40000>;
48 console-size = <0x10000>;
49 record-size = <0x10000>;
50 ftrace-size = <0x10000>;
51 pmsg-size = <0x20000>;
55 reg = <0 0x03400000 0 0xc00000>;
60 reg = <0x0 0x05000000 0x0 0x1a00000>;
71 pm8994_regulators: regulators-0 {
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml183 reg = <0x0c360000 0x10000>,
184 <0x0c370000 0x10000>,
185 <0x0c380000 0x10000>,
186 <0x0c390000 0x10000>;
203 reg = <0x03400000 0x10000>;
215 pinctrl-0 = <&sdmmc1_3v3>;
/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts25 PowerPC,5121@0 {
33 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
41 ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
42 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
43 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
44 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
45 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
46 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
48 flash@0,0 {
50 reg = <0 0x00000000 0x04000000>;
[all …]
/linux/drivers/video/fbdev/
H A Dau1200fb.c55 #define DEBUG 0
64 #define print_dbg(f, arg...) do {} while (0)
68 #define AU1200_LCD_FB_IOCTL 0x46FF
96 #define WIN_POSITION (1<< 0)
186 static int nohwcursor = 0;
213 { /* Index 0 */
214 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
215 /* mode_backcolor */ 0x006600ff,
216 /* mode_colorkey,msk*/ 0, 0,
219 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
[all …]
H A Dcg14.c51 #define CG14_MCR_INTENABLE_MASK 0x80
53 #define CG14_MCR_VIDENABLE_MASK 0x40
55 #define CG14_MCR_PIXMODE_MASK 0x30
57 #define CG14_MCR_TMR_MASK 0x0c
59 #define CG14_MCR_TMENABLE_MASK 0x02
60 #define CG14_MCR_RESET_SHIFT 0
61 #define CG14_MCR_RESET_MASK 0x01
63 #define CG14_REV_REVISION_MASK 0xf0
64 #define CG14_REV_IMPL_SHIFT 0
65 #define CG14_REV_IMPL_MASK 0x0f
[all …]
/linux/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/linux/include/sound/
H A Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/drivers/input/touchscreen/
H A Dhideep.c35 #define HIDEEP_EVENT_ADDR 0x240
38 #define HIDEEP_WORK_MODE 0x081e
39 #define HIDEEP_RESET_CMD 0x9800
48 #define HIDEEP_KEY_IDX_MASK 0x0f
51 #define HIDEEP_YRAM_BASE 0x40000000
52 #define HIDEEP_PERIPHERAL_BASE 0x50000000
53 #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000)
54 #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000)
55 #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000)
57 #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000)
[all …]

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