Lines Matching +full:0 +full:x03400000
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
15 #define INSN_HVCL 0x002b8000
17 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
18 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
19 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
20 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
21 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
29 #define ADDR_IMMSHIFT_ORI 0
38 break_op = 0x54,
42 b_op = 0x14,
43 bl_op = 0x15,
47 lu12iw_op = 0x0a,
48 lu32id_op = 0x0b,
49 pcaddi_op = 0x0c,
50 pcalau12i_op = 0x0d,
51 pcaddu12i_op = 0x0e,
52 pcaddu18i_op = 0x0f,
56 beqz_op = 0x10,
57 bnez_op = 0x11,
58 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
59 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
63 revb2h_op = 0x0c,
64 revb4h_op = 0x0d,
65 revb2w_op = 0x0e,
66 revbd_op = 0x0f,
67 revh2w_op = 0x10,
68 revhd_op = 0x11,
69 extwh_op = 0x16,
70 extwb_op = 0x17,
71 cpucfg_op = 0x1b,
72 iocsrrdb_op = 0x19200,
73 iocsrrdh_op = 0x19201,
74 iocsrrdw_op = 0x19202,
75 iocsrrdd_op = 0x19203,
76 iocsrwrb_op = 0x19204,
77 iocsrwrh_op = 0x19205,
78 iocsrwrw_op = 0x19206,
79 iocsrwrd_op = 0x19207,
80 llacqw_op = 0xe15e0,
81 screlw_op = 0xe15e1,
82 llacqd_op = 0xe15e2,
83 screld_op = 0xe15e3,
87 slliw_op = 0x81,
88 srliw_op = 0x89,
89 sraiw_op = 0x91,
93 sllid_op = 0x41,
94 srlid_op = 0x45,
95 sraid_op = 0x49,
99 addiw_op = 0x0a,
100 addid_op = 0x0b,
101 lu52id_op = 0x0c,
102 andi_op = 0x0d,
103 ori_op = 0x0e,
104 xori_op = 0x0f,
105 ldb_op = 0xa0,
106 ldh_op = 0xa1,
107 ldw_op = 0xa2,
108 ldd_op = 0xa3,
109 stb_op = 0xa4,
110 sth_op = 0xa5,
111 stw_op = 0xa6,
112 std_op = 0xa7,
113 ldbu_op = 0xa8,
114 ldhu_op = 0xa9,
115 ldwu_op = 0xaa,
116 flds_op = 0xac,
117 fsts_op = 0xad,
118 fldd_op = 0xae,
119 fstd_op = 0xaf,
123 llw_op = 0x20,
124 scw_op = 0x21,
125 lld_op = 0x22,
126 scd_op = 0x23,
127 ldptrw_op = 0x24,
128 stptrw_op = 0x25,
129 ldptrd_op = 0x26,
130 stptrd_op = 0x27,
134 jirl_op = 0x13,
135 beq_op = 0x16,
136 bne_op = 0x17,
137 blt_op = 0x18,
138 bge_op = 0x19,
139 bltu_op = 0x1a,
140 bgeu_op = 0x1b,
144 bstrinsd_op = 0x2,
145 bstrpickd_op = 0x3,
149 asrtle_op = 0x02,
150 asrtgt_op = 0x03,
151 addw_op = 0x20,
152 addd_op = 0x21,
153 subw_op = 0x22,
154 subd_op = 0x23,
155 nor_op = 0x28,
156 and_op = 0x29,
157 or_op = 0x2a,
158 xor_op = 0x2b,
159 orn_op = 0x2c,
160 andn_op = 0x2d,
161 sllw_op = 0x2e,
162 srlw_op = 0x2f,
163 sraw_op = 0x30,
164 slld_op = 0x31,
165 srld_op = 0x32,
166 srad_op = 0x33,
167 mulw_op = 0x38,
168 mulhw_op = 0x39,
169 mulhwu_op = 0x3a,
170 muld_op = 0x3b,
171 mulhd_op = 0x3c,
172 mulhdu_op = 0x3d,
173 divw_op = 0x40,
174 modw_op = 0x41,
175 divwu_op = 0x42,
176 modwu_op = 0x43,
177 divd_op = 0x44,
178 modd_op = 0x45,
179 divdu_op = 0x46,
180 moddu_op = 0x47,
181 ldxb_op = 0x7000,
182 ldxh_op = 0x7008,
183 ldxw_op = 0x7010,
184 ldxd_op = 0x7018,
185 stxb_op = 0x7020,
186 stxh_op = 0x7028,
187 stxw_op = 0x7030,
188 stxd_op = 0x7038,
189 ldxbu_op = 0x7040,
190 ldxhu_op = 0x7048,
191 ldxwu_op = 0x7050,
192 fldxs_op = 0x7060,
193 fldxd_op = 0x7068,
194 fstxs_op = 0x7070,
195 fstxd_op = 0x7078,
196 scq_op = 0x70ae,
197 amswapw_op = 0x70c0,
198 amswapd_op = 0x70c1,
199 amaddw_op = 0x70c2,
200 amaddd_op = 0x70c3,
201 amandw_op = 0x70c4,
202 amandd_op = 0x70c5,
203 amorw_op = 0x70c6,
204 amord_op = 0x70c7,
205 amxorw_op = 0x70c8,
206 amxord_op = 0x70c9,
207 ammaxw_op = 0x70ca,
208 ammaxd_op = 0x70cb,
209 amminw_op = 0x70cc,
210 ammind_op = 0x70cd,
211 ammaxwu_op = 0x70ce,
212 ammaxdu_op = 0x70cf,
213 amminwu_op = 0x70d0,
214 ammindu_op = 0x70d1,
215 amswapdbw_op = 0x70d2,
216 amswapdbd_op = 0x70d3,
217 amadddbw_op = 0x70d4,
218 amadddbd_op = 0x70d5,
219 amanddbw_op = 0x70d6,
220 amanddbd_op = 0x70d7,
221 amordbw_op = 0x70d8,
222 amordbd_op = 0x70d9,
223 amxordbw_op = 0x70da,
224 amxordbd_op = 0x70db,
225 ammaxdbw_op = 0x70dc,
226 ammaxdbd_op = 0x70dd,
227 ammindbw_op = 0x70de,
228 ammindbd_op = 0x70df,
229 ammaxdbwu_op = 0x70e0,
230 ammaxdbdu_op = 0x70e1,
231 ammindbwu_op = 0x70e2,
232 ammindbdu_op = 0x70e3,
233 fldgts_op = 0x70e8,
234 fldgtd_op = 0x70e9,
235 fldles_op = 0x70ea,
236 fldled_op = 0x70eb,
237 fstgts_op = 0x70ec,
238 fstgtd_op = 0x70ed,
239 fstles_op = 0x70ee,
240 fstled_op = 0x70ef,
241 ldgtb_op = 0x70f0,
242 ldgth_op = 0x70f1,
243 ldgtw_op = 0x70f2,
244 ldgtd_op = 0x70f3,
245 ldleb_op = 0x70f4,
246 ldleh_op = 0x70f5,
247 ldlew_op = 0x70f6,
248 ldled_op = 0x70f7,
249 stgtb_op = 0x70f8,
250 stgth_op = 0x70f9,
251 stgtw_op = 0x70fa,
252 stgtd_op = 0x70fb,
253 stleb_op = 0x70fc,
254 stleh_op = 0x70fd,
255 stlew_op = 0x70fe,
256 stled_op = 0x70ff,
260 alslw_op = 0x02,
261 alslwu_op = 0x03,
262 alsld_op = 0x16,
381 LOONGARCH_GPR_ZERO = 0,
462 if (ip->reg0i26_format.immediate_l == 0
463 && ip->reg0i26_format.immediate_h == 0)
471 if (ip->reg1i21_format.immediate_l == 0
472 && ip->reg1i21_format.immediate_h == 0)
483 if (ip->reg2i16_format.immediate == 0)
552 immediate_l = offset & 0xffff; \
554 immediate_h = offset & 0x3ff; \