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/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-apmixed.c48 PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
49 0, 0, 0x0108, 0, 0x0104),
50 PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
51 0, 0, 0, 0x0118, 0, 0x0114),
52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
53 0, 0, 0, 0x0128, 0, 0x0124),
54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
55 0x0700, 1, 0x0138, 0, 0x0134),
56 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
57 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
[all …]
H A Dclk-mt7622-apmixedsys.c49 .set_ofs = 0x8,
50 .clr_ofs = 0x8,
51 .sta_ofs = 0x8,
59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
60 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
62 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
63 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
64 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
65 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-msi-digivox-ii.c12 { 0x0302, KEY_NUMERIC_2 },
13 { 0x0303, KEY_UP }, /* up */
14 { 0x0304, KEY_NUMERIC_3 },
15 { 0x0305, KEY_CHANNELDOWN },
16 { 0x0308, KEY_NUMERIC_5 },
17 { 0x0309, KEY_NUMERIC_0 },
18 { 0x030b, KEY_NUMERIC_8 },
19 { 0x030d, KEY_DOWN }, /* down */
20 { 0x0310, KEY_NUMERIC_9 },
21 { 0x0311, KEY_NUMERIC_7 },
[all …]
H A Drc-dvico-portable.c12 { 0x0302, KEY_SETUP }, /* Profile */
13 { 0x0343, KEY_POWER2 },
14 { 0x0306, KEY_EPG },
15 { 0x035a, KEY_BACK },
16 { 0x0305, KEY_MENU },
17 { 0x0347, KEY_INFO },
18 { 0x0301, KEY_TAB },
19 { 0x0342, KEY_PREVIOUSSONG },/* Replay */
20 { 0x0349, KEY_VOLUMEUP },
21 { 0x0309, KEY_VOLUMEDOWN },
[all …]
H A Drc-leadtek-y04g0051.c12 { 0x0300, KEY_POWER2 },
13 { 0x0303, KEY_SCREEN },
14 { 0x0304, KEY_RIGHT },
15 { 0x0305, KEY_NUMERIC_1 },
16 { 0x0306, KEY_NUMERIC_2 },
17 { 0x0307, KEY_NUMERIC_3 },
18 { 0x0308, KEY_LEFT },
19 { 0x0309, KEY_NUMERIC_4 },
20 { 0x030a, KEY_NUMERIC_5 },
21 { 0x030b, KEY_NUMERIC_6 },
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl9039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_OFFSET_OUT_UPPER 0x0238
31 …_OFFSET_OUT_UPPER_VALUE 7:0
33 …_OFFSET_OUT 0x023c
34 …_OFFSET_OUT_VALUE 31:0
36 …_LAUNCH_DMA 0x0300
37 …_LAUNCH_DMA_SRC_INLINE 0:0
38 …_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000
39 …_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001
[all …]
H A Dcl5039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo74c1.c47 PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size, in nv84_bo_move_exec()
48 0x0308, upper_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
49 0x030c, lower_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
50 0x0310, upper_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
51 0x0314, lower_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
52 0x0318, 0x00000000 /* MODE_COPY, QUERY_NONE */); in nv84_bo_move_exec()
53 return 0; in nv84_bo_move_exec()
H A Dnouveau_bo90b5.c38 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_copy()
51 PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), in nvc0_bo_move_copy()
52 0x0310, lower_32_bits(src_offset), in nvc0_bo_move_copy()
53 0x0314, upper_32_bits(dst_offset), in nvc0_bo_move_copy()
54 0x0318, lower_32_bits(dst_offset), in nvc0_bo_move_copy()
55 0x031c, PAGE_SIZE, in nvc0_bo_move_copy()
56 0x0320, PAGE_SIZE, in nvc0_bo_move_copy()
57 0x0324, PAGE_SIZE, in nvc0_bo_move_copy()
58 0x0328, line_count); in nvc0_bo_move_copy()
59 PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); in nvc0_bo_move_copy()
[all …]
H A Dnouveau_bo85b5.c45 u64 src_offset = mem->vma[0].addr; in nva3_bo_move_copy()
58 PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), in nva3_bo_move_copy()
59 0x0310, lower_32_bits(src_offset), in nva3_bo_move_copy()
60 0x0314, upper_32_bits(dst_offset), in nva3_bo_move_copy()
61 0x0318, lower_32_bits(dst_offset), in nva3_bo_move_copy()
62 0x031c, PAGE_SIZE, in nva3_bo_move_copy()
63 0x0320, PAGE_SIZE, in nva3_bo_move_copy()
64 0x0324, PAGE_SIZE, in nva3_bo_move_copy()
65 0x0328, line_count); in nva3_bo_move_copy()
66 PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110); in nva3_bo_move_copy()
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_dw_hdmi.c17 #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
18 #define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
19 #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
29 { 35500000, 0x0003, 0x0344, 0x0328 },
30 { 44900000, 0x0003, 0x0285, 0x0128 },
31 { 71000000, 0x0002, 0x1184, 0x0314 },
32 { 90000000, 0x0002, 0x1144, 0x0114 },
33 { 140250000, 0x0001, 0x20c4, 0x030a },
34 { 182750000, 0x0001, 0x2084, 0x010a },
35 { 281250000, 0x0000, 0x0084, 0x0305 },
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h26 #define ixLCAC_MC0_CNTL 0x011C
27 #define ixLCAC_MC0_OVR_SEL 0x011D
28 #define ixLCAC_MC0_OVR_VAL 0x011E
29 #define ixLCAC_MC1_CNTL 0x011F
30 #define ixLCAC_MC1_OVR_SEL 0x0120
31 #define ixLCAC_MC1_OVR_VAL 0x0121
32 #define ixLCAC_MC2_CNTL 0x0122
33 #define ixLCAC_MC2_OVR_SEL 0x0123
34 #define ixLCAC_MC2_OVR_VAL 0x0124
35 #define ixLCAC_MC3_CNTL 0x0125
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmt8365-pm-domains.h42 .ctl_offs = 0x30c,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
74 .ctl_offs = 0x0304,
75 .pwr_sta_offs = 0x0180,
76 .pwr_sta2nd_offs = 0x0184,
86 .ctl_offs = 0x0314,
87 .pwr_sta_offs = 0x0180,
88 .pwr_sta2nd_offs = 0x0184,
101 .ctl_offs = 0x032c,
[all …]
/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
/linux/sound/soc/sof/mediatek/mt8195/
H A Dmt8195.h15 #define DSP_REG_BASE 0x10803000
16 #define SCP_CFGREG_BASE 0x10724000
17 #define DSP_SYSAO_BASE 0x1080C000
22 #define DSP_JTAGMUX 0x0000
23 #define DSP_ALTRESETVEC 0x0004
24 #define DSP_PDEBUGDATA 0x0008
25 #define DSP_PDEBUGBUS0 0x000c
26 #define PDEBUG_ENABLE BIT(0)
27 #define DSP_PDEBUGBUS1 0x0010
28 #define DSP_PDEBUGINST 0x0014
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx35-pinctrl.yaml74 PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
78 PAD_CTL_PUS_100K_DOWN (0 << 4)
82 PAD_CTL_ODE_CMOS (0 << 3)
84 PAD_CTL_DSE_NOMINAL (0 << 1)
87 PAD_CTL_SRE_FAST (1 << 0)
88 PAD_CTL_SRE_SLOW (0 << 0)
94 PAD_CTL_PUS_100K_DOWN (0 << 4)
99 PAD_CTL_DSE_LOW (0 << 1)
103 PAD_CTL_SRE_FAST (1 << 0)
104 PAD_CTL_SRE_SLOW (0 << 0)
[all …]
/linux/sound/firewire/tascam/
H A Dtascam.h103 #define TSCM_ADDR_BASE 0xffff00000000ull
105 #define TSCM_OFFSET_FIRMWARE_REGISTER 0x0000
106 #define TSCM_OFFSET_FIRMWARE_FPGA 0x0004
107 #define TSCM_OFFSET_FIRMWARE_ARM 0x0008
108 #define TSCM_OFFSET_FIRMWARE_HW 0x000c
110 #define TSCM_OFFSET_ISOC_TX_CH 0x0200
111 #define TSCM_OFFSET_UNKNOWN 0x0204
112 #define TSCM_OFFSET_START_STREAMING 0x0208
113 #define TSCM_OFFSET_ISOC_RX_CH 0x020c
114 #define TSCM_OFFSET_ISOC_RX_ON 0x0210 /* Little conviction. */
[all …]

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