| /linux/fs/hfsplus/ |
| H A D | tables.c | 24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5260.h | 15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
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| /linux/include/linux/mfd/wm8350/ |
| H A D | pmic.h | 19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| H A D | bmp.h | 12 return 0x0000; in bmp_version()
18 if (bmp_version(bios) >= 0x0300) in bmp_mem_init_table()
20 return 0x0000; in bmp_mem_init_table()
26 if (bmp_version(bios) >= 0x0300) in bmp_sdr_seq_table()
28 return 0x0000; in bmp_sdr_seq_table()
34 if (bmp_version(bios) >= 0x0300) in bmp_ddr_seq_table()
36 return 0x0000; in bmp_ddr_seq_table()
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| /linux/arch/arm/mach-omap2/ |
| H A D | prcm43xx.h | 15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
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| /linux/include/linux/mfd/wm831x/ |
| H A D | regulator.h | 14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/ |
| H A D | mxms.c | 42 case 0x0200: in mxms_version()
43 case 0x0201: in mxms_version()
44 case 0x0300: in mxms_version()
51 return 0x0000; in mxms_version()
70 u8 *mxms = mxms_data(mxm), sum = 0; in mxms_checksum()
84 if (*(u32 *)mxms != 0x5f4d584d) { in mxms_valid()
104 u8 type = desc[0] & 0x0f; in mxms_foreach()
105 u8 headerlen = 0; in mxms_foreach()
106 u8 recordlen = 0; in mxms_foreach()
107 u8 entries = 0; in mxms_foreach()
[all …]
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| /linux/drivers/net/wireless/broadcom/brcm80211/include/ |
| H A D | brcmu_d11.h | 20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
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| H A D | brcmu_wifi.h | 18 #define CH_UPPER_SB 0x01
19 #define CH_LOWER_SB 0x02
20 #define CH_EWA_VALID 0x04
32 #define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
42 #define WL_CHANSPEC_CHAN_MASK 0x00ff
43 #define WL_CHANSPEC_CHAN_SHIFT 0
45 #define WL_CHANSPEC_CTL_SB_MASK 0x0300
47 #define WL_CHANSPEC_CTL_SB_LOWER 0x0100
48 #define WL_CHANSPEC_CTL_SB_UPPER 0x0200
49 #define WL_CHANSPEC_CTL_SB_NONE 0x0300
[all …]
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| /linux/arch/arm/mach-mv78xx0/ |
| H A D | bridge-regs.h | 8 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
9 #define L2_WRITETHROUGH 0x00020000
11 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
12 #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
13 #define SOFT_RESET_OUT_EN 0x00000004
15 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
16 #define SOFT_RESET 0x00000001
18 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
20 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
21 #define IRQ_CAUSE_ERR_OFF 0x0000
[all …]
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| /linux/drivers/net/wireless/marvell/libertas/ |
| H A D | radiotap.h | 17 0)
19 #define IEEE80211_FC_VERSION_MASK 0x0003
20 #define IEEE80211_FC_TYPE_MASK 0x000c
21 #define IEEE80211_FC_TYPE_MGT 0x0000
22 #define IEEE80211_FC_TYPE_CTL 0x0004
23 #define IEEE80211_FC_TYPE_DATA 0x0008
24 #define IEEE80211_FC_SUBTYPE_MASK 0x00f0
25 #define IEEE80211_FC_TOFROMDS_MASK 0x0300
26 #define IEEE80211_FC_TODS_MASK 0x0100
27 #define IEEE80211_FC_FROMDS_MASK 0x0200
[all …]
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| /linux/arch/arm/mach-dove/ |
| H A D | bridge-regs.h | 9 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
11 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
12 #define CPU_CTRL_PCIE0_LINK 0x00000001
13 #define CPU_RESET 0x00000002
14 #define CPU_CTRL_PCIE1_LINK 0x00000008
16 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
17 #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
18 #define SOFT_RESET_OUT_EN 0x00000004
20 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21 #define SOFT_RESET 0x00000001
[all …]
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| /linux/drivers/tty/serial/ |
| H A D | dz.h | 18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
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| /linux/drivers/media/firewire/ |
| H A D | firedtv-rc.c | 21 /* code from device: 0x4501...0x451f */
55 /* code from device: 0x4540...0x4542 */
65 /* code from device: 0x0300...0x031f */
67 [0x00] = KEY_POWER,
68 [0x01] = KEY_SLEEP,
69 [0x02] = KEY_STOP,
70 [0x03] = KEY_OK,
71 [0x04] = KEY_RIGHT,
72 [0x05] = KEY_1,
73 [0x06] = KEY_2,
[all …]
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| /linux/include/media/i2c/ |
| H A D | m52790.h | 14 #define M52790_SW1_IN_MASK 0x0003
15 #define M52790_SW1_IN_TUNER 0x0000
16 #define M52790_SW1_IN_V2 0x0001
17 #define M52790_SW1_IN_V3 0x0002
18 #define M52790_SW1_IN_V4 0x0003
21 #define M52790_SW1_YCMIX 0x0004
26 #define M52790_SW2_IN_MASK 0x0300
27 #define M52790_SW2_IN_TUNER 0x0000
28 #define M52790_SW2_IN_V2 0x0100
29 #define M52790_SW2_IN_V3 0x0200
[all …]
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| /linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | port.h | 16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
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| /linux/drivers/staging/vt6656/ |
| H A D | desc.h | 40 #define RSR_ADDRUNI 0x00
46 #define RSR_ADDROK BIT(0)
55 #define NEWRSR_BCNHITAID0 BIT(0)
63 #define TSR_VALID BIT(0)
65 #define FIFOCTL_AUTO_FB_1 0x1000
66 #define FIFOCTL_AUTO_FB_0 0x0800
67 #define FIFOCTL_GRPACK 0x0400
68 #define FIFOCTL_11GA 0x0300
69 #define FIFOCTL_11GB 0x0200
70 #define FIFOCTL_11B 0x0100
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | sgtl5000.h | 14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
[all …]
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| /linux/include/linux/mmc/ |
| H A D | sdio_ids.h | 13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
[all …]
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt7622-apmixedsys.c | 49 .set_ofs = 0x8,
50 .clr_ofs = 0x8,
51 .sta_ofs = 0x8,
59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
60 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
62 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
63 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
64 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
65 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
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| H A D | clk-mt2712-apmixedsys.c | 53 { .div = 0, .freq = MT2712_PLL_FMAX },
62 { .div = 0, .freq = MT2712_PLL_FMAX },
71 { .div = 0, .freq = MT2712_PLL_FMAX },
80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
84 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
[all …]
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| /linux/drivers/staging/vt6655/ |
| H A D | desc.h | 24 #define B_OWNED_BY_HOST 0
27 #define RSR_ADDRBROAD 0x80
28 #define RSR_ADDRMULTI 0x40
29 #define RSR_ADDRUNI 0x00
30 #define RSR_IVLDTYP 0x20
31 #define RSR_IVLDLEN 0x10 /* invalid len (> 2312 byte) */
32 #define RSR_BSSIDOK 0x08
33 #define RSR_CRCOK 0x04
34 #define RSR_BCNSSIDOK 0x02
35 #define RSR_ADDROK 0x01
[all …]
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
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| /linux/arch/sh/include/mach-common/mach/ |
| H A D | highlander.h | 6 #define PA_NORFLASH_ADDR 0x00000000
7 #define PA_NORFLASH_SIZE 0x04000000
10 #define PA_BCR 0xa4000000 /* FPGA */
13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
16 #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
17 #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
18 #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
[all …]
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| /linux/include/video/ |
| H A D | tgafb.h | 20 #define TGA_TYPE_8PLANE 0
28 #define TGA_ROM_OFFSET 0x0000000
29 #define TGA_REGS_OFFSET 0x0100000
30 #define TGA_8PLANE_FB_OFFSET 0x0200000
31 #define TGA_24PLANE_FB_OFFSET 0x0804000
32 #define TGA_24PLUSZ_FB_OFFSET 0x1004000
34 #define TGA_FOREGROUND_REG 0x0020
35 #define TGA_BACKGROUND_REG 0x0024
36 #define TGA_PLANEMASK_REG 0x0028
37 #define TGA_PIXELMASK_ONESHOT_REG 0x002c
[all …]
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