Lines Matching +full:0 +full:x0300

53 	{ .div = 0, .freq = MT2712_PLL_FMAX },
62 { .div = 0, .freq = MT2712_PLL_FMAX },
71 { .div = 0, .freq = MT2712_PLL_FMAX },
80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
84 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
87 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
88 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
89 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
90 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
91 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
92 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
93 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
94 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
95 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
96 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
97 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
98 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
99 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
100 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
101 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
102 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
103 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
104 PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
105 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
106 PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
107 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
108 PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
109 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
132 return 0; in clk_mt2712_apmixed_probe()