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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
H A Dimx94-pinfunc.h10 #define IMX94_DSE_X1 0x2
11 #define IMX94_DSE_X2 0x6
12 #define IMX94_DSE_X3 0xe
13 #define IMX94_DSE_X4 0x1e
14 #define IMX94_DSE_X5 0x3e
15 #define IMX94_DSE_X6 0x7e
18 #define IMX94_FSEL_FAST 0x180
19 #define IMX94_FSEL_SLOW 0x100
22 #define IMX94_PU_ENABLE 0x200
23 #define IMX94_PU_DISABLE 0x0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx7ulp-iomuxc1.yaml66 PAD_CTL_DSE_STD (0 << 6)
68 PAD_CTL_PUSH_PULL (0 << 5)
70 PAD_CTL_SRE_STD (0 << 2)
71 PAD_CTL_PE (1 << 0)
91 reg = <0x40ac0000 0x1000>;
95 0x000c 0x0248 0x4 0x1 0x1
96 0x0008 0x024c 0x4 0x1 0x1
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h38 #define IPW_CSR_INTR 0x0008
39 #define IPW_CSR_INTR_MASK 0x000c
40 #define IPW_CSR_INDIRECT_ADDR 0x0010
41 #define IPW_CSR_INDIRECT_DATA 0x0014
42 #define IPW_CSR_AUTOINC_ADDR 0x0018
43 #define IPW_CSR_AUTOINC_DATA 0x001c
44 #define IPW_CSR_RST 0x0020
45 #define IPW_CSR_CTL 0x0024
46 #define IPW_CSR_IO 0x0030
47 #define IPW_CSR_TX_BASE 0x0200
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am654-idk.dtso17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
27 pinctrl-0 = <&icssg0_rgmii_pins_default>;
50 interrupts = <24 0 2>, <25 1 3>;
53 dmas = <&main_udmap 0xc100>, /* egress slice 0 */
54 <&main_udmap 0xc101>, /* egress slice 0 */
55 <&main_udmap 0xc102>, /* egress slice 0 */
56 <&main_udmap 0xc103>, /* egress slice 0 */
57 <&main_udmap 0xc104>, /* egress slice 1 */
58 <&main_udmap 0xc105>, /* egress slice 1 */
[all …]
H A Dk3-am642-phyboard-electra-rdk.dts45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
67 interrupts = <24 0 2>, <25 1 3>;
78 dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
79 <&main_pktdma 0xc101 15>, /* egress slice 0 */
80 <&main_pktdma 0xc102 15>, /* egress slice 0 */
81 <&main_pktdma 0xc103 15>, /* egress slice 0 */
[all …]
H A Dk3-am65-iot2050-common.dtsi45 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
46 alignment = <0x1000>;
52 reg = <0 0xa0000000 0 0x100000>;
58 reg = <0 0xa0100000 0 0xf00000>;
64 reg = <0 0xa1000000 0 0x100000>;
70 reg = <0 0xa1100000 0 0xf00000>;
75 reg = <0x00 0xa2000000 0x00 0x00200000>;
76 alignment = <0x1000>;
82 reg = <0x00 0xa2200000 0x00 0x1000>;
90 pinctrl-0 = <&leds_pins_default>;
[all …]
H A Dk3-am642-sk.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
68 reg = <0x00 0xa1000000 0x00 0x100000>;
74 reg = <0x00 0xa1100000 0x00 0xf00000>;
80 reg = <0x00 0xa2000000 0x00 0x100000>;
86 reg = <0x00 0xa2100000 0x00 0xf00000>;
92 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am642-evm.dts42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 alignment = <0x1000>;
58 reg = <0x00 0xa0000000 0x00 0x100000>;
64 reg = <0x00 0xa0100000 0x00 0xf00000>;
70 reg = <0x00 0xa1000000 0x00 0x100000>;
76 reg = <0x00 0xa1100000 0x00 0xf00000>;
82 reg = <0x00 0xa2000000 0x00 0x100000>;
88 reg = <0x00 0xa2100000 0x00 0xf00000>;
94 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am642-tqma64xxl-mbax4xxl.dts50 pinctrl-0 = <&mcu_gpio_keys_pins>;
62 pinctrl-0 = <&mcu_gpio_leds_pins>;
64 led-0 {
79 pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>;
81 interrupts = <24 0 2>, <25 1 3>;
83 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
84 <&main_pktdma 0xc201 15>, /* egress slice 0 */
85 <&main_pktdma 0xc202 15>, /* egress slice 0 */
86 <&main_pktdma 0xc203 15>, /* egress slice 0 */
87 <&main_pktdma 0xc204 15>, /* egress slice 1 */
[all …]
/freebsd/sys/x86/iommu/
H A Damd_reg.h38 #define AMDIOMMU_DEVTAB_BASE 0x0000
39 #define AMDIOMMU_CMDBUF_BASE 0x0008
40 #define AMDIOMMU_EVNTLOG_BASE 0x0010
41 #define AMDIOMMU_CTRL 0x0018
42 #define AMDIOMMU_EXCL_BASE 0x0020
43 #define AMDIOMMU_EXCL_RANGE 0x0028
44 #define AMDIOMMU_EFR 0x0030
45 #define AMDIOMMU_PPRLOG_BASE 0x0038
46 #define AMDIOMMU_HWEV_UPPER 0x0040
47 #define AMDIOMMU_HWEV_LOWER 0x0048
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dreg.h8 #define REG_SYS_FUNC_EN 0x0002
15 #define BIT_FEN_BB_RSTB BIT(0)
18 #define REG_SYS_PW_CTRL 0x0004
21 #define REG_APS_FSMCO 0x0004
25 #define REG_SYS_CLK_CTRL 0x0008
28 #define REG_SYS_CLKR 0x0008
33 #define REG_RSV_CTRL 0x001C
34 #define DISABLE_PI 0x3
35 #define ENABLE_PI 0x2
37 #define BIT_WLMCU_IOIF BIT(0)
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
40 clock-frequency = <0>;
44 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
54 clock-frequency = <0>;
[all …]
/freebsd/sys/dev/vt/font/
H A Dvt_font_default.c38 0x00, 0x00, 0x7e, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x7e,
39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
40 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10,
41 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
42 0x00, 0x24, 0x24, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
43 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x24, 0x24, 0x7e, 0x24, 0x24,
44 0x7e, 0x24, 0x24, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x7c,
45 0x92, 0x90, 0x90, 0x7c, 0x12, 0x12, 0x92, 0x7c, 0x10, 0x10, 0x00, 0x00,
46 0x00, 0x00, 0x64, 0x94, 0x68, 0x08, 0x10, 0x10, 0x20, 0x2c, 0x52, 0x4c,
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x24, 0x24, 0x18, 0x30, 0x4a,
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-16BE-rev1 0x00 = 0x0000
2 0x01 = 0x0100
3 0x02 = 0x0200
4 0x03 = 0x0300
5 0x04 = 0x0400
6 0x05 = 0x0500
7 0x06 = 0x0600
8 0x07 = 0x0700
9 0x08 = 0x0800
10 0x09 = 0x0900
[all …]
H A DUTF-16LE-rev1 0x00 = 0x0000
2 0x01 = 0x0001
3 0x02 = 0x0002
4 0x03 = 0x0003
5 0x04 = 0x0004
6 0x05 = 0x0005
7 0x06 = 0x0006
8 0x07 = 0x0007
9 0x08 = 0x0008
10 0x09 = 0x0009
[all …]
/freebsd/share/i18n/csmapper/GB/
H A DGB18030%UCS@BMP.src30 SRC_ZONE 0x81-0x84 / 0x30-0x39 / 0x81-0xFE / 0x30-0x39 / 8
32 DST_ILSEQ 0xFFFE
71 # for (i = 0; i < ncharset; ++i) {
74 # charsets[i], charsets[i + off], 0, &norm);
75 # if (ret != 0)
86 # for (i = 0; i < ncharset; ++i)
96 # for (i = 0; i < ncharset; i += 2) {
98 # if (ret == 0) {
101 # if (ret == 0 && tmp == src)
105 # return 0;
[all …]
H A DUCS@BMP%GB18030.src30 SRC_ZONE 0x0080-0xFFFD
32 DST_INVALID 0xFFFFFFFF
36 0x0080 = 0x81308130
37 0x0081 = 0x81308131
38 0x0082 = 0x81308132
39 0x0083 = 0x81308133
40 0x0084 = 0x81308134
41 0x0085 = 0x81308135
42 0x0086 = 0x81308136
43 0x0087 = 0x81308137
[all …]
/freebsd/tools/tools/locale/etc/charmaps/
H A DGB18030.TXT5 0x03 0x0003
6 0x04 0x0004
7 0x05 0x0005
8 0x06 0x0006
9 0x07 0x0007
10 0x08 0x0008
11 0x09 0x0009
12 0x0A 0x000A
13 0x0B 0x000B
14 0x0C 0x000C
[all …]

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