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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i3c/
H A Dsnps,dw-i3c-master.yaml50 #size-cells = <0>;
51 reg = <0x02000 0x1000>;
52 interrupts = <0>;
57 reg = <0x57 0x0 0x10>;
58 pagesize = <0x8>;
H A Dsnps,dw-i3c-master.txt15 - #size-cells: shall be set to 0
31 #size-cells = <0>;
32 reg = <0x02000 0x1000>;
33 interrupts = <0>;
38 reg = <0x57 0x0 0x10>;
39 pagesize = <0x8>;
/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_priv.h34 { 0x421, 0x0f }, { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 },
35 { 0x431, 0x00 }, { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 },
36 { 0x435, 0x05 }, { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 },
37 { 0x43d, 0x05 }, { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d },
38 { 0x441, 0x01 }, { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 },
39 { 0x446, 0x00 }, { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 },
40 { 0x44a, 0x0f }, { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 },
41 { 0x44e, 0x00 }, { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 },
42 { 0x452, 0x0f }, { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 },
43 { 0x461, 0x66 }, { 0x4c8, 0x3f }, { 0x4c9, 0xff }, { 0x4cc, 0xff },
[all …]
/freebsd/contrib/ntp/include/
H A Dhopf6039.h13 #define HOPF_CNTR_MEM_LEN 0x7f
14 #define HOPF_DATA_MEM_LEN 0x3ff /* this is our memory size */
23 #define HIWORD(l) ((WORD)(((DWORD)(l) >> 16) & 0xFFFF))
25 #define HIBYTE(w) ((BYTE)(((WORD)(w) >> 8) & 0xFF))
29 #define HOPF_CLOCK_CMD_MASK 0xff000
31 #define HOPF_CLOCK_GET_LOCAL 0x10000
32 #define HOPF_CLOCK_GET_UTC 0x20000
33 #define HOPF_CLOCK_GET_ANTENNA 0x30000
34 #define HOPF_CLOCK_GET_DIFFERENCE 0x40000
35 #define HOPF_CLOCK_GET_VERSION 0x50000
[all …]
/freebsd/include/
H A Ddlfcn.h42 #define RTLD_MODEMASK 0x3
43 #define RTLD_GLOBAL 0x100 /* Make symbols globally available. */
44 #define RTLD_LOCAL 0 /* Opposite of RTLD_GLOBAL, and the default. */
45 #define RTLD_TRACE 0x200 /* Trace loaded objects and exit. */
46 #define RTLD_NODELETE 0x01000 /* Do not remove members. */
47 #define RTLD_NOLOAD 0x02000 /* Do not load if not already loaded. */
48 #define RTLD_DEEPBIND 0x04000 /* Put symbols from the dso ahead of
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DMinidumpConstants.def3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 HANDLE_MDMP_STREAM_TYPE(0x0003, ThreadList)
40 HANDLE_MDMP_STREAM_TYPE(0x0004, ModuleList)
41 HANDLE_MDMP_STREAM_TYPE(0x0005, MemoryList)
42 HANDLE_MDMP_STREAM_TYPE(0x0006, Exception)
43 HANDLE_MDMP_STREAM_TYPE(0x0007, SystemInfo)
44 HANDLE_MDMP_STREAM_TYPE(0x0008, ThreadExList)
45 HANDLE_MDMP_STREAM_TYPE(0x0009, Memory64List)
46 HANDLE_MDMP_STREAM_TYPE(0x000a, CommentA)
47 HANDLE_MDMP_STREAM_TYPE(0x000b, CommentW)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
26 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
65 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
66 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
67 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
68 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
69 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
70 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ in __mt7921_reg_addr()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_vf.h45 #define IXGBE_VFCTRL 0x00000
46 #define IXGBE_VFSTATUS 0x00008
47 #define IXGBE_VFLINKS 0x00010
48 #define IXGBE_VFFRTIMER 0x00048
49 #define IXGBE_VFRXMEMWRAP 0x03190
50 #define IXGBE_VTEICR 0x00100
51 #define IXGBE_VTEICS 0x00104
52 #define IXGBE_VTEIMS 0x00108
53 #define IXGBE_VTEIMC 0x0010C
54 #define IXGBE_VTEIAC 0x00110
[all …]
/freebsd/sys/contrib/openzfs/include/os/freebsd/spl/sys/
H A Dvnode.h51 #define NOCRED ((struct ucred *)0) /* no credential available */
75 #define vn_vfswlock(vp) (0)
76 #define vn_vfsunlock(vp) do { } while (0)
81 (vp)->v_object->resident_page_count > 0)
87 int flags = sync ? OBJPC_SYNC : 0; in vn_flush_cached_data()
89 vm_object_page_clean(vp->v_object, 0, 0, flags); in vn_flush_cached_data()
101 #define vnevent_create(vp, ct) do { } while (0)
102 #define vnevent_link(vp, ct) do { } while (0)
103 #define vnevent_remove(vp, dvp, name, ct) do { } while (0)
104 #define vnevent_rmdir(vp, dvp, name, ct) do { } while (0)
[all …]
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_reset.c57 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
58 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
59 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
60 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
61 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
62 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
63 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
64 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
65 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
66 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml67 enum: [ 0, 1, 2 ]
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
82 bits[3:0] trigger type and level flags.
150 "^v2m@[0-9a-f]+$":
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
[all …]
/freebsd/crypto/openssl/include/internal/
H A Dffc.h26 # define FFC_PARAM_TYPE_DSA 0
33 #define FFC_PARAM_MODE_VERIFY 0
37 #define FFC_PARAM_RET_STATUS_FAILED 0
43 # define FFC_PARAM_FLAG_VALIDATE_PQ 0x01
44 # define FFC_PARAM_FLAG_VALIDATE_G 0x02
47 #define FFC_PARAM_FLAG_VALIDATE_LEGACY 0x04
53 # define FFC_CHECK_P_NOT_PRIME 0x00001
54 # define FFC_CHECK_P_NOT_SAFE_PRIME 0x00002
55 # define FFC_CHECK_UNKNOWN_GENERATOR 0x00004
56 # define FFC_CHECK_NOT_SUITABLE_GENERATOR 0x00008
[all …]
/freebsd/usr.bin/calendar/
H A Dcalendar.h64 #define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
67 #define F_NONE 0x00000
68 #define F_MONTH 0x00001
69 #define F_DAYOFWEEK 0x00002
70 #define F_DAYOFMONTH 0x00004
71 #define F_MODIFIERINDEX 0x00008
72 #define F_MODIFIEROFFSET 0x00010
73 #define F_SPECIALDAY 0x00020
74 #define F_ALLMONTH 0x00040
75 #define F_ALLDAY 0x00080
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd/crypto/openssl/crypto/
H A Dsparcv9cap.c24 unsigned int OPENSSL_sparcv9cap_P[2] = { SPARCV9_TICK_PRIVILEGED, 0 };
40 if (OPENSSL_sparcv9cap_P[0] & SPARCV9_TICK_PRIVILEGED) in OPENSSL_rdtsc()
44 return 0; in OPENSSL_rdtsc()
52 if ((OPENSSL_sparcv9cap_P[0] & (SPARCV9_TICK_PRIVILEGED | SPARCV9_BLK)) == in OPENSSL_instrument_bus()
56 return 0; in OPENSSL_instrument_bus()
61 if ((OPENSSL_sparcv9cap_P[0] & (SPARCV9_TICK_PRIVILEGED | SPARCV9_BLK)) == in OPENSSL_instrument_bus2()
65 return 0; in OPENSSL_instrument_bus2()
90 static int trigger = 0; in OPENSSL_cpuid_setup()
97 OPENSSL_sparcv9cap_P[0] = strtoul(e, NULL, 0); in OPENSSL_cpuid_setup()
99 OPENSSL_sparcv9cap_P[1] = strtoul(e + 1, NULL, 0); in OPENSSL_cpuid_setup()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/freebsd/sys/dev/aic7xxx/
H A Daic79xx.h68 #define FALSE 0
73 #define ALL_CHANNELS '\0'
74 #define ALL_TARGETS_MASK 0xFFFF
75 #define INITIATOR_WILDCARD (~0)
76 #define SCB_LIST_NULL 0xFF00
78 #define QOUTFIFO_ENTRY_VALID 0x80
79 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
86 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
98 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
101 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
[all...]
/freebsd/sys/netpfil/ipfilter/netinet/
H A Dip_state.h89 #define is_send is_tcp.ts_data[0].td_end
91 #define is_maxswin is_tcp.ts_data[0].td_maxwin
93 #define is_maxsend is_tcp.ts_data[0].td_maxend
95 #define is_swinscale is_tcp.ts_data[0].td_winscale
97 #define is_swinflags is_tcp.ts_data[0].td_winflags
101 #define is_ifpin is_ifp[0]
106 #define IS_WSPORT SI_W_SPORT /* 0x00100 */
107 #define IS_WDPORT SI_W_DPORT /* 0x00200 */
108 #define IS_WSADDR SI_W_SADDR /* 0x00400 */
109 #define IS_WDADDR SI_W_DADDR /* 0x00800 */
[all …]
/freebsd/contrib/lib9p/
H A Dgenacl.h145 #define L9P_ACE_READ_DATA 0x00001
146 #define L9P_ACE_LIST_DIRECTORY 0x00001 /* same as READ_DATA */
147 #define L9P_ACE_WRITE_DATA 0x00002
148 #define L9P_ACE_ADD_FILE 0x00002 /* same as WRITE_DATA */
149 #define L9P_ACE_APPEND_DATA 0x00004
150 #define L9P_ACE_ADD_SUBDIRECTORY 0x00004 /* same as APPEND_DATA */
151 #define L9P_ACE_READ_NAMED_ATTRS 0x00008
152 #define L9P_ACE_WRITE_NAMED_ATTRS 0x00010
153 #define L9P_ACE_EXECUTE 0x00020
154 #define L9P_ACE_DELETE_CHILD 0x00040
[all …]
/freebsd/sys/sys/
H A Dtty.h68 #define TF_NOPREFIX 0x00001 /* Don't prepend "tty" to device name. */
69 #define TF_INITLOCK 0x00002 /* Create init/lock state devices. */
70 #define TF_CALLOUT 0x00004 /* Create "cua" devices. */
71 #define TF_OPENED_IN 0x00008 /* "tty" node is in use. */
72 #define TF_OPENED_OUT 0x00010 /* "cua" node is in use. */
73 #define TF_OPENED_CONS 0x00020 /* Device in use as console. */
75 #define TF_GONE 0x00040 /* Device node is gone. */
76 #define TF_OPENCLOSE 0x00080 /* Device is in open()/close(). */
77 #define TF_ASYNC 0x00100 /* Asynchronous I/O enabled. */
78 #define TF_LITERAL 0x00200 /* Accept the next character literally. */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210.h22 #define AR5210_MAGIC 0x19980124
24 #if 0
30 #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32 #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36 #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37 #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]

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