Home
last modified time | relevance | path

Searched +full:0 +full:x01c00000 (Results 1 – 25 of 44) sorted by relevance

12

/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/linux/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
H A Dboard-mtx1.c41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); in mtx1_reset()
57 alchemy_gpio_direction_output(204, 0); in board_setup()
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR); in board_setup()
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ in board_setup()
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ in board_setup()
72 alchemy_gpio_direction_output(212, 0); /* red off */ in board_setup()
105 .dev_id = "mtx1-wdt.0",
115 .id = 0,
144 .size = 0x01C00000,
145 .offset = 0,
[all …]
/linux/arch/arm/mach-davinci/
H A Dhardware.h23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
H A Ddevices-da8xx.c27 #define DA8XX_TPCC_BASE 0x01c00000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
31 #define DA8XX_I2C0_BASE 0x01c22000
32 #define DA8XX_RTC_BASE 0x01c23000
33 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
34 #define DA8XX_MMCSD0_BASE 0x01c40000
35 #define DA8XX_SPI0_BASE 0x01c41000
36 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon-common.yaml69 reg = <0x01c00000 0x1000>;
/linux/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sc8180x.yaml89 reg = <0 0x01c00000 0 0x3000>,
90 <0 0x60000000 0 0xf1d>,
91 <0 0x60000f20 0 0xa8>,
92 <0 0x60001000 0 0x1000>,
93 <0 0x60100000 0 0x100000>;
99 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
100 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
102 bus-range = <0x00 0xff>;
104 linux,pci-domain = <0>;
147 interrupt-map-mask = <0 0 0 0x7>;
[all …]
H A Dqcom,pcie-sm8350.yaml94 reg = <0 0x01c00000 0 0x3000>,
95 <0 0x60000000 0 0xf1d>,
96 <0 0x60000f20 0 0xa8>,
97 <0 0x60001000 0 0x1000>,
98 <0 0x60100000 0 0x100000>;
100 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
101 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
103 bus-range = <0x00 0xff>;
105 linux,pci-domain = <0>;
142 interrupt-map-mask = <0 0 0 0x7>;
[all …]
H A Dqcom,pcie-sm8150.yaml95 reg = <0 0x01c00000 0 0x3000>,
96 <0 0x60000000 0 0xf1d>,
97 <0 0x60000f20 0 0xa8>,
98 <0 0x60001000 0 0x1000>,
99 <0 0x60100000 0 0x100000>;
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
102 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
104 bus-range = <0x00 0xff>;
106 linux,pci-domain = <0>;
137 interrupt-map-mask = <0 0 0 0x7>;
[all …]
H A Dqcom,pcie-sa8775p.yaml101 reg = <0x0 0x01c00000 0x0 0x3000>,
102 <0x0 0x40000000 0x0 0xf20>,
103 <0x0 0x40000f20 0x0 0xa8>,
104 <0x0 0x40001000 0x0 0x4000>,
105 <0x0 0x40100000 0x0 0x100000>,
106 <0x0 0x01c03000 0x0 0x1000>;
108 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
109 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
111 bus-range = <0x00 0xff>;
113 linux,pci-domain = <0>;
[all …]
H A Dqcom,pcie-sm8550.yaml104 reg = <0 0x01c00000 0 0x3000>,
105 <0 0x60000000 0 0xf1d>,
106 <0 0x60000f20 0 0xa8>,
107 <0 0x60001000 0 0x1000>,
108 <0 0x60100000 0 0x100000>;
110 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
111 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
113 bus-range = <0x00 0xff>;
115 linux,pci-domain = <0>;
150 interrupt-map-mask = <0 0 0 0x7>;
[all …]
H A Dqcom,pcie-sm8250.yaml104 reg = <0 0x01c00000 0 0x3000>,
105 <0 0x60000000 0 0xf1d>,
106 <0 0x60000f20 0 0xa8>,
107 <0 0x60001000 0 0x1000>,
108 <0 0x60100000 0 0x100000>,
109 <0 0x01c03000 0 0x1000>;
111 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
112 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
114 bus-range = <0x00 0xff>;
116 linux,pci-domain = <0>;
[all …]
/linux/Documentation/devicetree/bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml62 "^regulators@[0-9a-f]+$":
121 reg = <0x01c00000 0x30>;
126 sram_a: sram@0 {
128 reg = <0x00000000 0xc000>;
131 ranges = <0 0x00000000 0xc000>;
135 reg = <0x8000 0x4000>;
143 reg = <0x3000000 0x1000>;
150 reg = <0x3000150 0x4>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
80 reg = <0x01c00000 0x1000>;
87 reg = <0x00018000 0x1c000>;
90 ranges = <0 0x00018000 0x1c000>;
92 ve_sram: sram-section@0 {
95 reg = <0x000000 0x1c000>;
102 reg = <0x01c0e000 0x1000>;
113 reg = <0x01c15000 0x1000>;
[all …]
/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h60 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
84 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
/linux/drivers/net/ethernet/intel/ixgbevf/
H A Ddefines.h8 #define IXGBE_DEV_ID_82599_VF 0x10ED
9 #define IXGBE_DEV_ID_X540_VF 0x1515
10 #define IXGBE_DEV_ID_X550_VF 0x1565
11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E
15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
19 #define IXGBE_DEV_ID_E610_VF 0x57AD
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
H A Dsun8i-v3s.dtsi72 #size-cells = <0>;
74 cpu@0 {
77 reg = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
126 reg = <0x01000000 0x10000>;
138 reg = <0x01100000 0x100000>;
139 clocks = <&display_clocks 0>,
143 resets = <&display_clocks 0>;
147 #size-cells = <0>;
[all …]
/linux/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/linux/include/video/
H A Dnewport.h34 #define DM1_PLANES 0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Daf9005-fe.c54 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff)))) in af9005_write_word_agc()
57 (u8) ((value & 0x300) >> 8)); in af9005_write_word_agc()
71 case 0: in af9005_read_word_agc()
72 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0; in af9005_read_word_agc()
75 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0; in af9005_read_word_agc()
78 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0; in af9005_read_word_agc()
81 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0; in af9005_read_word_agc()
87 return 0; in af9005_read_word_agc()
112 if ((temp & 1) == 0) in af9005_is_fecmon_available()
116 return 0; in af9005_is_fecmon_available()
[all …]

12