1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 251dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher #ifndef _IXGBEVF_DEFINES_H_ 5dee1ad47SJeff Kirsher #define _IXGBEVF_DEFINES_H_ 6dee1ad47SJeff Kirsher 7dee1ad47SJeff Kirsher /* Device IDs */ 8dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_VF 0x10ED 9dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_X540_VF 0x1515 1047068b0dSEmil Tantilov #define IXGBE_DEV_ID_X550_VF 0x1565 1147068b0dSEmil Tantilov #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 121d94f987SDon Skidmore #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 13dee1ad47SJeff Kirsher 14b4363fbdSKY Srinivasan #define IXGBE_DEV_ID_82599_VF_HV 0x152E 15b4363fbdSKY Srinivasan #define IXGBE_DEV_ID_X540_VF_HV 0x1530 16b4363fbdSKY Srinivasan #define IXGBE_DEV_ID_X550_VF_HV 0x1564 17b4363fbdSKY Srinivasan #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 18b4363fbdSKY Srinivasan 19dee1ad47SJeff Kirsher #define IXGBE_VF_IRQ_CLEAR_MASK 7 2056e94095SAlexander Duyck #define IXGBE_VF_MAX_TX_QUEUES 8 2156e94095SAlexander Duyck #define IXGBE_VF_MAX_RX_QUEUES 8 2256e94095SAlexander Duyck 2356e94095SAlexander Duyck /* DCB define */ 2456e94095SAlexander Duyck #define IXGBE_VF_MAX_TRAFFIC_CLASS 8 25dee1ad47SJeff Kirsher 26dee1ad47SJeff Kirsher /* Link speed */ 27dee1ad47SJeff Kirsher typedef u32 ixgbe_link_speed; 28dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 29dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 3031a1b375SGreg Rose #define IXGBE_LINK_SPEED_100_FULL 0x0008 31dee1ad47SJeff Kirsher 32dee1ad47SJeff Kirsher #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 33dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 34dee1ad47SJeff Kirsher #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 35dee1ad47SJeff Kirsher #define IXGBE_LINKS_UP 0x40000000 36dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_82599 0x30000000 37dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 38dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 3931a1b375SGreg Rose #define IXGBE_LINKS_SPEED_100_82599 0x10000000 40dee1ad47SJeff Kirsher 41dee1ad47SJeff Kirsher /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 42dee1ad47SJeff Kirsher #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 43dee1ad47SJeff Kirsher #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 44dee1ad47SJeff Kirsher #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 45dee1ad47SJeff Kirsher 46dee1ad47SJeff Kirsher /* Interrupt Vector Allocation Registers */ 47dee1ad47SJeff Kirsher #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 48dee1ad47SJeff Kirsher 49dee1ad47SJeff Kirsher #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 50dee1ad47SJeff Kirsher 51dee1ad47SJeff Kirsher /* Receive Config masks */ 52dee1ad47SJeff Kirsher #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 53dee1ad47SJeff Kirsher #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 54dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 55dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 56dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 57dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_RLPML_EN 0x00008000 58dee1ad47SJeff Kirsher 59dee1ad47SJeff Kirsher /* DCA Control */ 608d055cc0SJacob Keller #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 61dee1ad47SJeff Kirsher 62dee1ad47SJeff Kirsher /* PSRTYPE bit definitions */ 63dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_TCPHDR 0x00000010 64dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_UDPHDR 0x00000020 65dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 66dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 67dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_L2HDR 0x00001000 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher /* SRRCTL bit definitions */ 70dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 71dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_RDMTS_SHIFT 22 72dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 73dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DROP_EN 0x10000000 74dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 75dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 76dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 77dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 78dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 79dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 80dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 81dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 82dee1ad47SJeff Kirsher 83dee1ad47SJeff Kirsher /* Receive Descriptor bit definitions */ 84dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 85dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 86dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 87dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 88dee1ad47SJeff Kirsher #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 89dee1ad47SJeff Kirsher #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 90dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 91dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 92dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 93dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 94dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 95dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 96dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 97dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 98dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 99dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 100dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 101dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 102dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 103dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 104dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 105dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 106dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 107dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 108dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 109dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ 110dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 111dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 112dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 113dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 114dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 115dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 116dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 117dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 118dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 119dee1ad47SJeff Kirsher #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 120dee1ad47SJeff Kirsher #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 121dee1ad47SJeff Kirsher #define IXGBE_RXD_PRI_SHIFT 13 122dee1ad47SJeff Kirsher #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 123dee1ad47SJeff Kirsher #define IXGBE_RXD_CFI_SHIFT 12 124dee1ad47SJeff Kirsher 125dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 126dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 127dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 128dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 129dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ 130dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 131dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 132dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 133dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 134dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 135dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 136adef9a26SShannon Nelson #define IXGBE_RXDADV_STAT_SECP 0x00020000 /* IPsec/MACsec pkt found */ 137dee1ad47SJeff Kirsher 138dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 139dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 140adef9a26SShannon Nelson #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 141adef9a26SShannon Nelson #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 142adef9a26SShannon Nelson #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 143adef9a26SShannon Nelson #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 144dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 145dee1ad47SJeff Kirsher #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 146dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 147dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSCCNT_SHIFT 17 148dee1ad47SJeff Kirsher #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 149dee1ad47SJeff Kirsher #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 150dee1ad47SJeff Kirsher #define IXGBE_RXDADV_SPH 0x8000 151dee1ad47SJeff Kirsher 1521e1429d6SFan Du /* RSS Hash results */ 1531e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 1541e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 1551e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 1561e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 1571e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 1581e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 1591e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 1601e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 1611e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 1621e1429d6SFan Du #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 1631e1429d6SFan Du 164dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 165dee1ad47SJeff Kirsher IXGBE_RXD_ERR_CE | \ 166dee1ad47SJeff Kirsher IXGBE_RXD_ERR_LE | \ 167dee1ad47SJeff Kirsher IXGBE_RXD_ERR_PE | \ 168dee1ad47SJeff Kirsher IXGBE_RXD_ERR_OSE | \ 169dee1ad47SJeff Kirsher IXGBE_RXD_ERR_USE) 170dee1ad47SJeff Kirsher 171dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 172dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_CE | \ 173dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_LE | \ 174dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_PE | \ 175dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_OSE | \ 176dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_USE) 177dee1ad47SJeff Kirsher 178dee1ad47SJeff Kirsher #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 179dee1ad47SJeff Kirsher #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 180dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 181dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 182dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 183dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 184dec0d8e4SJeff Kirsher #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor ext (0 = legacy) */ 185dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 186dee1ad47SJeff Kirsher #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 18729d37fa1SEmil Tantilov #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS) 188dee1ad47SJeff Kirsher 189dee1ad47SJeff Kirsher /* Transmit Descriptor - Advanced */ 190dee1ad47SJeff Kirsher union ixgbe_adv_tx_desc { 191dee1ad47SJeff Kirsher struct { 192dee1ad47SJeff Kirsher __le64 buffer_addr; /* Address of descriptor's data buf */ 193dee1ad47SJeff Kirsher __le32 cmd_type_len; 194dee1ad47SJeff Kirsher __le32 olinfo_status; 195dee1ad47SJeff Kirsher } read; 196dee1ad47SJeff Kirsher struct { 197dee1ad47SJeff Kirsher __le64 rsvd; /* Reserved */ 198dee1ad47SJeff Kirsher __le32 nxtseq_seed; 199dee1ad47SJeff Kirsher __le32 status; 200dee1ad47SJeff Kirsher } wb; 201dee1ad47SJeff Kirsher }; 202dee1ad47SJeff Kirsher 203dee1ad47SJeff Kirsher /* Receive Descriptor - Advanced */ 204dee1ad47SJeff Kirsher union ixgbe_adv_rx_desc { 205dee1ad47SJeff Kirsher struct { 206dee1ad47SJeff Kirsher __le64 pkt_addr; /* Packet buffer address */ 207dee1ad47SJeff Kirsher __le64 hdr_addr; /* Header buffer address */ 208dee1ad47SJeff Kirsher } read; 209dee1ad47SJeff Kirsher struct { 210dee1ad47SJeff Kirsher struct { 211dee1ad47SJeff Kirsher union { 212dee1ad47SJeff Kirsher __le32 data; 213dee1ad47SJeff Kirsher struct { 214dee1ad47SJeff Kirsher __le16 pkt_info; /* RSS, Pkt type */ 215dee1ad47SJeff Kirsher __le16 hdr_info; /* Splithdr, hdrlen */ 216dee1ad47SJeff Kirsher } hs_rss; 217dee1ad47SJeff Kirsher } lo_dword; 218dee1ad47SJeff Kirsher union { 219dee1ad47SJeff Kirsher __le32 rss; /* RSS Hash */ 220dee1ad47SJeff Kirsher struct { 221dee1ad47SJeff Kirsher __le16 ip_id; /* IP id */ 222dee1ad47SJeff Kirsher __le16 csum; /* Packet Checksum */ 223dee1ad47SJeff Kirsher } csum_ip; 224dee1ad47SJeff Kirsher } hi_dword; 225dee1ad47SJeff Kirsher } lower; 226dee1ad47SJeff Kirsher struct { 227dee1ad47SJeff Kirsher __le32 status_error; /* ext status/error */ 228dee1ad47SJeff Kirsher __le16 length; /* Packet length */ 229dee1ad47SJeff Kirsher __le16 vlan; /* VLAN tag */ 230dee1ad47SJeff Kirsher } upper; 231dee1ad47SJeff Kirsher } wb; /* writeback */ 232dee1ad47SJeff Kirsher }; 233dee1ad47SJeff Kirsher 234dee1ad47SJeff Kirsher /* Context descriptors */ 235dee1ad47SJeff Kirsher struct ixgbe_adv_tx_context_desc { 236dee1ad47SJeff Kirsher __le32 vlan_macip_lens; 2377f68d430SShannon Nelson __le32 fceof_saidx; 238dee1ad47SJeff Kirsher __le32 type_tucmd_mlhl; 239dee1ad47SJeff Kirsher __le32 mss_l4len_idx; 240dee1ad47SJeff Kirsher }; 241dee1ad47SJeff Kirsher 242dee1ad47SJeff Kirsher /* Adv Transmit Descriptor Config Masks */ 243dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 244dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 245dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 246dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 247dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 248dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 249dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 250dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 251dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 252dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 253dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 254dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 255dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 256dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 257dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 258adef9a26SShannon Nelson #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 259adef9a26SShannon Nelson #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 /* ESP Encrypt Enable */ 260dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 26170a10e25SAlexander Duyck #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 262dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 263adef9a26SShannon Nelson #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 264dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 265dee1ad47SJeff Kirsher IXGBE_ADVTXD_POPTS_SHIFT) 266dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 267dee1ad47SJeff Kirsher IXGBE_ADVTXD_POPTS_SHIFT) 268dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 269dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 270dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 271dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 272dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 273dee1ad47SJeff Kirsher 274dee1ad47SJeff Kirsher /* Interrupt register bitmasks */ 275dee1ad47SJeff Kirsher 276dee1ad47SJeff Kirsher #define IXGBE_EITR_CNT_WDIS 0x80000000 2775f3600ebSAlexander Duyck #define IXGBE_MAX_EITR 0x00000FF8 2785f3600ebSAlexander Duyck #define IXGBE_MIN_EITR 8 279dee1ad47SJeff Kirsher 280dee1ad47SJeff Kirsher /* Error Codes */ 281dee1ad47SJeff Kirsher #define IXGBE_ERR_INVALID_MAC_ADDR -1 282dee1ad47SJeff Kirsher #define IXGBE_ERR_RESET_FAILED -2 28331186785SAlexander Duyck #define IXGBE_ERR_INVALID_ARGUMENT -3 284887a3203SRadoslaw Tyl #define IXGBE_ERR_CONFIG -4 285887a3203SRadoslaw Tyl #define IXGBE_ERR_MBX -5 286887a3203SRadoslaw Tyl #define IXGBE_ERR_TIMEOUT -6 287*c8692598SRadoslaw Tyl #define IXGBE_ERR_PARAM -7 288dee1ad47SJeff Kirsher 289de02decbSDon Skidmore /* Transmit Config masks */ 290de02decbSDon Skidmore #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 291de02decbSDon Skidmore #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 292de02decbSDon Skidmore #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 293de02decbSDon Skidmore 2948d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ 2958d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ 2968d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ 2978d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ 2988d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 2998d055cc0SJacob Keller #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 300de02decbSDon Skidmore 3018d055cc0SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 3028d055cc0SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 3038d055cc0SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 3048d055cc0SJacob Keller #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 305de02decbSDon Skidmore 306dee1ad47SJeff Kirsher #endif /* _IXGBEVF_DEFINES_H_ */ 307