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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/freebsd/tools/test/iconv/ref/
H A DCP12581 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DTCVN5712-11 0x0000 = 0x0000
2 0x0001 = 0x0000
3 0x0002 = 0x1EE4
4 0x0003 = 0x0003
5 0x0004 = 0x1EEA
6 0x0005 = 0x1EEC
7 0x0006 = 0x1EEE
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DCP11631 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DVISCII1 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x1EB2
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x1EB4
7 0x0006 = 0x1EAA
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DCP11291 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
/freebsd/share/i18n/csmapper/TCVN/
H A DTCVN5712-1%UCS.src5 SRC_ZONE 0x0000-0xF3FF
7 DST_ILSEQ 0xFFFE
46 0x0000 = 0x0000
47 0x0001 = 0x0000
48 0x0001 = 0x00DA
49 0x0002 = 0x1EE4
50 0x0003 = 0x0003
51 0x0004 = 0x1EEA
52 0x0005 = 0x1EEC
53 0x0006 = 0x1EEE
[all …]
H A DVISCII%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
48 # positions (first char is at 0x02) so the table goes from 0x00 to 0xff.
50 0x00 = 0x0000
51 0x01 = 0x0001
52 0x02 = 0x1EB2
53 0x03 = 0x0003
54 0x04 = 0x0004
55 0x05 = 0x1EB4
56 0x06 = 0x1EAA
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am6548-iot2050-advanced-common.dtsi21 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
28 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
29 AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
30 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
31 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
32 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
33 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
34 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
35 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
36 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwm8903.txt21 default is 0.
28 performed. If any entry has the value 0xffffffff, that GPIO's
62 reg = <0x1a>;
73 micdet-cfg = <0>;
76 0x0600 /* DMIC_LR, output */
77 0x0680 /* DMIC_DAT, input */
78 0x0000 /* GPIO, output, low */
79 0x0200 /* Interrupt, output */
80 0x01a0 /* BCLK, input, active high */
H A Dwlf,wm8903.yaml48 default: 0
63 If any entry has the value 0xffffffff, that GPIO's
91 #size-cells = <0>;
95 reg = <0x1a>;
106 micdet-cfg = <0>;
109 0x0600 /* DMIC_LR, output */
110 0x0680 /* DMIC_DAT, input */
111 0x0000 /* GPIO, output, low */
112 0x0200 /* Interrupt, output */
113 0x01a0 /* BCLK, input, active high */
/freebsd/share/i18n/csmapper/CP/
H A DCP1163%UCS.src30 SRC_ZONE 0x00-0xFF
32 DST_ILSEQ 0xFFFE
43 0x00 - 0xA3 = 0x0000 -
44 0xA4 = 0x20AC
45 0xA5 - 0xA7 = 0x00A5 -
46 0xA8 = 0x0153
47 0xA9 - 0xB3 = 0x00A9 -
48 0xB4 = 0x0178
49 0xB5 - 0xB7 = 0x00B5 -
50 0xB8 = 0x0152
[all …]
H A DCP1129%UCS.src30 SRC_ZONE 0x00-0xFF
32 DST_ILSEQ 0xFFFE
43 0x00 - 0x9F = 0x0000 -
44 0xA0 = 0x00A0
45 0xA1 = 0x00A1
46 0xA2 = 0x00A2
47 0xA3 = 0x00A3
48 0xA4 = 0x00A4
49 0xA5 = 0x00A5
50 0xA6 = 0x00A6
[all …]
H A DCP1258%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
27 # Column #2 is the Unicode (in hex as 0xXXXX)
32 0x00 = 0x0000
33 0x01 = 0x0001
34 0x02 = 0x0002
35 0x03 = 0x0003
36 0x04 = 0x0004
37 0x05 = 0x0005
38 0x06 = 0x0006
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_memac_mii_acc.h39 #define MDIO_CFG_CLK_DIV_MASK 0x0080ff80
41 #define MDIO_CFG_HOLD_MASK 0x0000001c
42 #define MDIO_CFG_ENC45 0x00000040
43 #define MDIO_CFG_READ_ERR 0x00000002
44 #define MDIO_CFG_BSY 0x00000001
47 #define MDIO_CTL_READ 0x00008000
49 #define MDIO_DATA_BSY 0x80000000
52 #define PHY_SGMII_CR_PHY_RESET 0x8000
53 #define PHY_SGMII_CR_RESET_AN 0x0200
54 #define PHY_SGMII_CR_DEF_VAL 0x1140
[all …]
H A Dfsl_fman_dtsec_mii_acc.h40 #define MIIMCFG_RESET_MGMT 0x80000000
41 #define MIIMCFG_MGNTCLK_MASK 0x00000007
42 #define MIIMCFG_MGNTCLK_SHIFT 0
45 #define MIIMCOM_SCAN_CYCLE 0x00000002
46 #define MIIMCOM_READ_CYCLE 0x00000001
50 #define MIIMADD_PHY_ADDR_MASK 0x00001f00
52 #define MIIMADD_REG_ADDR_SHIFT 0
53 #define MIIMADD_REG_ADDR_MASK 0x0000001f
56 #define MIIMIND_BUSY 0x00000001
60 #define PHY_CR_PHY_RESET 0x8000
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/
H A Dmemac.h63 default: bitMask = 0;break;}
90 #define PHY_MDIO_ADDR 0
93 #define PHY_SGMII_CR_PHY_RESET 0x8000
94 #define PHY_SGMII_CR_RESET_AN 0x0200
95 #define PHY_SGMII_CR_DEF_VAL 0x1140
96 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
97 #define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
98 #define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
99 #define PHY_SGMII_IF_MODE_AN 0x0002
100 #define PHY_SGMII_IF_MODE_SGMII 0x0001
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]

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