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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am642-tqma64xxl.dtsi19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
48 reg = <0x00 0xa1000000 0x00 0x100000>;
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
60 reg = <0x00 0xa2000000 0x00 0x100000>;
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
72 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am68-sk-som.dtsi16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000003 0x80000000>;
26 reg = <0x00 0x9e800000 0x00 0x01800000>;
32 reg = <0x00 0xa0000000 0x00 0x100000>;
38 reg = <0x00 0xa0100000 0x00 0xf00000>;
44 reg = <0x00 0xa1000000 0x00 0x100000>;
50 reg = <0x00 0xa1100000 0x00 0xf00000>;
56 reg = <0x00 0xa2000000 0x00 0x100000>;
62 reg = <0x00 0xa2100000 0x00 0xf00000>;
68 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am62-phycore-som.dtsi31 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
41 reg = <0x00 0x9ca00000 0x00 0x00100000>;
42 record-size = <0x8000>;
43 console-size = <0x8000>;
44 ftrace-size = <0x00>;
45 pmsg-size = <0x8000>;
49 reg = <0x00 0x9e780000 0x00 0x80000>;
50 alignment = <0x1000>;
55 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
56 alignment = <0x1000>;
[all …]
H A Dk3-am62a-phycore-som.dtsi31 pinctrl-0 = <&leds_pins_default>;
33 led-0 {
44 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
56 size = <0x00 0x24000000>;
57 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
62 reg = <0x00 0x9e780000 0x00 0x80000>;
63 alignment = <0x1000>;
68 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
69 alignment = <0x1000>;
75 reg = <0x00 0x9c900000 0x00 0x01e00000>;
[all …]
H A Dk3-am64-phycore-som.dtsi29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
38 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
39 alignment = <0x1000>;
45 reg = <0x00 0xa0000000 0x00 0x100000>;
51 reg = <0x00 0xa0100000 0x00 0xf00000>;
57 reg = <0x00 0xa1000000 0x00 0x100000>;
63 reg = <0x00 0xa1100000 0x00 0xf00000>;
69 reg = <0x00 0xa2000000 0x00 0x100000>;
75 reg = <0x00 0xa2100000 0x00 0xf00000>;
81 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am67a-beagley-ai.dts32 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
33 <0x00000008 0x80000000 0x00000000 0x80000000>;
44 reg = <0x00 0x9e780000 0x00 0x80000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>;
55 reg = <0x00 0xa0100000 0x00 0xf00000>;
84 pinctrl-0 = <&vdd_3v3_sd_pins_default>;
97 pinctrl-0 = <&vdd_sd_dv_pins_default>;
103 states = <1800000 0x0>,
104 <3300000 0x1>;
129 pinctrl-0 = <&led_pins_default>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-qcs404.yaml27 - description: PCIe 0 PIPE clock (optional)
28 - description: DSI phy instance 0 dsi clock
29 - description: DSI phy instance 0 byte clock
54 reg = <0x01800000 0x80000>;
H A Dqcom,ipq5332-gcc.yaml47 reg = <0x01800000 0x80000>;
H A Dqcom,gcc-ipq8074.yaml50 reg = <0x01800000 0x80000>;
H A Dqcom,gcc-ipq6018.yaml52 reg = <0x01800000 0x80000>;
H A Dqcom,gcc-msm8909.yaml31 - description: DSI phy instance 0 dsi clock
32 - description: DSI phy instance 0 byte clock
56 reg = <0x01800000 0x80000>;
60 clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
H A Dqcom,ipq9574-gcc.yaml54 reg = <0x01800000 0x80000>;
H A Dqcom,ipq5018-gcc.yaml51 reg = <0x01800000 0x80000>;
H A Dqcom,gcc-msm8953.yaml58 reg = <0x01800000 0x80000>;
62 <&dsi0_phy 0>,
64 <&dsi1_phy 0>;
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/freebsd/sys/arm/ti/
H A Dti_adcreg.h30 #define ADC_REVISION 0x000
31 #define ADC_REV_SCHEME_MSK 0xc0000000
33 #define ADC_REV_FUNC_MSK 0x0fff0000
35 #define ADC_REV_RTL_MSK 0x0000f800
37 #define ADC_REV_MAJOR_MSK 0x00000700
39 #define ADC_REV_CUSTOM_MSK 0x000000c0
41 #define ADC_REV_MINOR_MSK 0x0000003f
42 #define ADC_SYSCFG 0x010
43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0
45 #define ADC_IRQSTATUS_RAW 0x024
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-l-50.dts18 reg = <0x00000000 0x20000000>;
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
70 reg = <0x20>;
75 /* Three GPIOs from 0x21 exp. are undescribed in dts:
85 reg = <0x21>;
92 reg = <0x30>;
128 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
208 reg = <0x08>;
214 #size-cells = <0>;
215 reg = <0x10>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416desc.h29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
68 uint32_t ds_ctl0; /* DMA control 0 */
104 #define AR_FrameLen 0x00000fff
105 #define AR_VirtMoreFrag 0x00001000
106 #define AR_TxCtlRsvd00 0x0000e000
107 #define AR_XmitPower 0x003f0000
109 #define AR_RTSEnable 0x00400000
110 #define AR_VEOL 0x00800000
111 #define AR_ClrDestMask 0x01000000
112 #define AR_TxCtlRsvd01 0x1e000000
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_chan.c69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | in r12a_write_txpower_ht()
99 /* 1SS, MCS 0..3 */ in r12a_write_txpower_vht()
101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) | in r12a_write_txpower_vht()
102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) | in r12a_write_txpower_vht()
103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) | in r12a_write_txpower_vht()
104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)])); in r12a_write_txpower_vht()
108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) | in r12a_write_txpower_vht()
109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) | in r12a_write_txpower_vht()
110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) | in r12a_write_txpower_vht()
111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)])); in r12a_write_txpower_vht()
[all …]
/freebsd/sys/dev/bhnd/siba/
H A Dsibareg.h47 #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
64 * [0x0000-0x0dff] core registers
65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
66 * [0x0f00-0x0fff] SIBA_R0 registers
69 #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
71 #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
83 #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
84 #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq5018.dtsi21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 cache-size = <0x80000>;
89 reg = <0x0 0x40000000 0x0 0x0>;
108 reg = <0x0 0x4a800000 0x0 0x200000>;
113 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]

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