Lines Matching +full:0 +full:x01800000

21 			#clock-cells = <0>;
26 			#clock-cells = <0>;
32 		#size-cells = <0>;
34 		CPU0: cpu@0 {
37 			reg = <0x0>;
47 			reg = <0x1>;
57 			cache-size = <0x80000>;
89 		reg = <0x0 0x40000000 0x0 0x0>;
108 			reg = <0x0 0x4a800000 0x0 0x200000>;
113 			reg = <0x0 0x4aa00000 0x0 0x100000>;
119 			reg = <0x0 0x4ab00000 0x0 0x100000>;
126 			reg = <0x0 0x4ac00000 0x0 0x200000>;
131 	soc: soc@0 {
135 		ranges = <0 0 0 0xffffffff>;
139 			reg = <0x0005b000 0x120>;
145 			#phy-cells = <0>;
152 			reg = <0x01000000 0x300000>;
156 			gpio-ranges = <&tlmm 0 0 47>;
170 			reg = <0x01800000 0x80000>;
173 				 <0>,
174 				 <0>,
175 				 <0>,
176 				 <0>,
177 				 <0>,
178 				 <0>,
179 				 <0>;
186 			reg = <0x01905000 0x20000>;
192 			reg = <0x7804000 0x1000>;
209 			reg = <0x07884000 0x1d000>;
214 			qcom,ee = <0>;
219 			reg = <0x078af000 0x200>;
230 			#size-cells = <0>;
231 			reg = <0x078b5000 0x600>;
243 			reg = <0x08af8800 0x400>;
268 				reg = <0x08a00000 0xe000>;
276 				snps,hird-threshold = /bits/ 8 <0x0>;
284 			reg = <0x0b000000 0x1000>,  /* GICD */
285 			      <0x0b002000 0x2000>,  /* GICC */
286 			      <0x0b001000 0x1000>,  /* GICH */
287 			      <0x0b004000 0x2000>;  /* GICV */
293 			ranges = <0 0x0b00a000 0x1ffa>;
295 			v2m0: v2m@0 {
297 				reg = <0x00000000 0xff8>;
303 				reg = <0x00001000 0xff8>;
310 			reg = <0x0b017000 0x40>;
318 			reg = <0x0b111000 0x1000>;
327 			reg = <0x0b116000 0x40>;
328 			#clock-cells = <0>;
335 			reg = <0x0b120000 0x1000>;
341 				reg = <0x0b121000 0x1000>,
342 				      <0x0b122000 0x1000>;
345 				frame-number = <0>;
349 				reg = <0xb123000 0x1000>;
358 				reg = <0x0b124000 0x1000>;
363 				reg = <0x0b125000 0x1000>;
370 				reg = <0x0b126000 0x1000>;
377 				reg = <0x0b127000 0x1000>;
384 				reg = <0x0b128000 0x1000>;