| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
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| H A D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
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| H A D | imx6sll-pinfunc.h | 15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
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| H A D | imx7d-pinfunc.h | 14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
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| H A D | imx6sx-pinfunc.h | 13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
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| H A D | imx93-pinfunc.h | 13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | fsl,imx8ulp-pinctrl.yaml | 73 reg = <0x298c0000 0x10000>;
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
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| /freebsd/sys/contrib/dev/mediatek/mt76/ |
| H A D | sdio.h | 12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
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| /freebsd/sys/dev/usb/net/ |
| H A D | if_ruereg.h | 29 #define RUE_CONFIG_IDX 0 /* config number 1 */
30 #define RUE_IFACE_IDX 0
32 #define RUE_INTR_PKTLEN 0x8
38 #define RUE_IDR0 0x0120
39 #define RUE_IDR1 0x0121
40 #define RUE_IDR2 0x0122
41 #define RUE_IDR3 0x0123
42 #define RUE_IDR4 0x0124
43 #define RUE_IDR5 0x0125
45 #define RUE_MAR0 0x0126
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| /freebsd/share/i18n/csmapper/ISO-8859/ |
| H A D | ISO-8859-10%UCS.src | 5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-10 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
52 # 1.1 corrected mistake in mapping of 0xA4
61 0x00-0x7F = 0x00-
62 0x80 = 0x0080
63 0x81 = 0x0081
64 0x82 = 0x0082
65 0x83 = 0x0083
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| H A D | ISO-8859-4%UCS.src | 5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-4 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
61 0x00-0x7F = 0x00-
62 0x80 = 0x0080
63 0x81 = 0x0081
64 0x82 = 0x0082
65 0x83 = 0x0083
66 0x84 = 0x0084
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| /freebsd/tools/test/iconv/ref/ |
| H A D | ISO8859-10 | 1 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
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| H A D | ISO8859-4 | 1 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | rtw8822bu.c | 12 { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb812, 0xff, 0xff, 0xff),
14 { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb82c, 0xff, 0xff, 0xff),
16 { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x2102, 0xff, 0xff, 0xff),
18 { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb822, 0xff, 0xff, 0xff),
20 { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xc822, 0xff, 0xff, 0xff),
22 { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xd822, 0xff, 0xff, 0xff),
24 { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xe822, 0xff, 0xff, 0xff),
26 { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xf822, 0xff, 0xff, 0xff),
28 { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb81a, 0xff, 0xff, 0xff),
30 { USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1841, 0xff, 0xff, 0xff),
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| /freebsd/contrib/libxo/libxo/ |
| H A D | xo_wcwidth.h | 73 int min = 0; in xo_bisearch()
76 if (ucs < table[0].first || ucs > table[max].last) in xo_bisearch()
77 return 0; in xo_bisearch()
88 return 0; in xo_bisearch()
95 * - The null character (U+0000) has a column width of 0.
102 * column width of 0.
107 * database) and ZERO WIDTH SPACE (U+200B) have a column width of 0.
110 * have a column width of 0.
130 { 0x0300, 0x036F }, { 0x0483, 0x0486 }, { 0x0488, 0x0489 }, in xo_wcwidth()
131 { 0x0591, 0x05BD }, { 0x05BF, 0x05BF }, { 0x05C1, 0x05C2 }, in xo_wcwidth()
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| /freebsd/contrib/ncurses/ncurses/ |
| H A D | wcwidth.h | 81 int min = 0; in bisearch()
84 if (ucs < table[0].first || ucs > table[max].last) in bisearch()
85 return 0; in bisearch()
96 return 0; in bisearch()
103 * - The null character (U+0000) has a column width of 0.
110 * column width of 0.
115 * database) and ZERO WIDTH SPACE (U+200B) have a column width of 0.
118 * have a column width of 0.
137 { 0x0300, 0x036F }, { 0x0483, 0x0486 }, { 0x0488, 0x0489 }, in mk_wcwidth()
138 { 0x0591, 0x05BD }, { 0x05BF, 0x05BF }, { 0x05C1, 0x05C2 }, in mk_wcwidth()
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | scientific | 10 0 string MTZ\040 MTZ reflection file
19 0 string EZD_MAP NEWEZD Electron Density Map
22 0 string/c :-)\040Origin BRIX Electron Density Map
23 >170 string >0 , Sigma:%.12s
24 #>4 string >0 %.178s
39 0 string R-AXIS4\ \ \ R-Axis Area Detector Image:
41 >>768 lelong >0 Size=%dx
42 >>772 lelong >0 \b%d
44 >>768 belong >0 Size=%dx
45 >>772 belong >0 \b%d
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| /freebsd/sys/arm/xilinx/ |
| H A D | zy7_slcr.h | 43 #define ZY7_SCLR_SCL 0x0000
44 #define ZY7_SLCR_LOCK 0x0004
45 #define ZY7_SLCR_LOCK_MAGIC 0x767b
46 #define ZY7_SLCR_UNLOCK 0x0008
47 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
48 #define ZY7_SLCR_LOCKSTA 0x000c
51 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
52 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
53 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
54 #define ZY7_SLCR_PLL_CTRL_RESET (1 << 0)
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| /freebsd/tools/tools/locale/etc/charmaps/ |
| H A D | ISO8859-4.TXT | 32 # Column #1 is the ISO/IEC 8859-4 code (in hex as 0xXX)
33 # Column #2 is the Unicode (in hex as 0xXXXX)
49 0x00 0x0000 # NULL
50 0x01 0x0001 # START OF HEADING
51 0x02 0x0002 # START OF TEXT
52 0x03 0x0003 # END OF TEXT
53 0x04 0x0004 # END OF TRANSMISSION
54 0x05 0x0005 # ENQUIRY
55 0x06 0x0006 # ACKNOWLEDGE
56 0x07 0x0007 # BELL
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| /freebsd/sys/dev/ral/ |
| H A D | rt2560reg.h | 19 #define RT2560_DEFAULT_RSSI_CORR 0x79
36 #define RT2560_CSR0 0x0000 /* ASIC version number */
37 #define RT2560_CSR1 0x0004 /* System control */
38 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
39 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
40 #define RT2560_CSR5 0x0014 /* BSSID 0 */
41 #define RT2560_CSR6 0x0018 /* BSSID 1 */
42 #define RT2560_CSR7 0x001c /* Interrupt source */
43 #define RT2560_CSR8 0x0020 /* Interrupt mask */
44 #define RT2560_CSR9 0x0024 /* Maximum frame length */
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| /freebsd/sys/dev/safe/ |
| H A D | safereg.h | 37 #define BS_BAR 0x10 /* DMA base address register */
38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-evm.dts | 41 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
50 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
51 alignment = <0x1000>;
57 reg = <0x0
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| H A D | k3-am642-sk.dts | 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x0
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap5-cm-t54.dts | 17 reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */
66 #phy-cells = <0>;
73 #phy-cells = <0>;
91 pinctrl-0 = <&lcd_pins>;
105 hsync-active = <0>;
106 vsync-active = <0>;
125 pinctrl-0 = <&hdmi_conn_pins>;
141 #size-cells = <0>;
143 port@0 {
144 reg = <0>;
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