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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
H A Dprm2xxx.h35 #define OMAP2_PRCM_REVISION_OFFSET 0x0000
36 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
37 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
38 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
40 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
41 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
42 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
43 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
45 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
46 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/include/soc/spacemit/
H A Dk1-syscon.h21 #define APBS_PLL1_SWCR1 0x100
22 #define APBS_PLL1_SWCR2 0x104
23 #define APBS_PLL1_SWCR3 0x108
24 #define APBS_PLL2_SWCR1 0x118
25 #define APBS_PLL2_SWCR2 0x11c
26 #define APBS_PLL2_SWCR3 0x120
27 #define APBS_PLL3_SWCR1 0x124
28 #define APBS_PLL3_SWCR2 0x128
29 #define APBS_PLL3_SWCR3 0x12c
32 #define MPMU_POSR 0x0010
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dathub_v3_0.c31 #define regATHUB_MISC_CNTL_V3_0_1 0x00d7
32 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0
33 #define regATHUB_MISC_CNTL_V3_3_0 0x00d8
34 #define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0
41 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_get_cg_cntl()
42 case IP_VERSION(3, 0, 1): in athub_v3_0_get_cg_cntl()
43 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1); in athub_v3_0_get_cg_cntl()
45 case IP_VERSION(3, 3, 0): in athub_v3_0_get_cg_cntl()
46 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0); in athub_v3_0_get_cg_cntl()
49 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL); in athub_v3_0_get_cg_cntl()
[all …]
/linux/drivers/media/usb/gspca/
H A Dspca501.c29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
[all …]
/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac-mii.dtso23 #size-cells = <0>;
25 mdio@0 {
26 reg = <0x0>;
28 #size-cells = <0>;
40 AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */
41 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */
42 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */
43 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */
44 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */
45 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dilt.c23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-crc16.c24 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
25 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
26 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
27 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
28 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
29 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
30 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
31 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
32 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
33 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_5_0_0_offset.h27 // base address: 0x3c80
28 …HDP_MMHUB_TLVL 0x0000
29 …ne mmHDP_MMHUB_TLVL_BASE_IDX 0
30 …HDP_MMHUB_UNITID 0x0001
31 …ne mmHDP_MMHUB_UNITID_BASE_IDX 0
32 …HDP_NONSURFACE_BASE 0x0040
33 …ne mmHDP_NONSURFACE_BASE_BASE_IDX 0
34 …HDP_NONSURFACE_INFO 0x0041
35 …ne mmHDP_NONSURFACE_INFO_BASE_IDX 0
36 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_7_0_0_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0008
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0009
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_4_4_2_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_5_2_1_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_4_0_offset.h27 // base address: 0x3c80
28 #define mmHDP_MMHUB_TLVL 0x0000
29 #define mmHDP_MMHUB_TLVL_BASE_IDX 0
30 #define mmHDP_MMHUB_UNITID 0x0001
31 #define mmHDP_MMHUB_UNITID_BASE_IDX 0
32 #define mmHDP_NONSURFACE_BASE 0x0040
33 #define mmHDP_NONSURFACE_BASE_BASE_IDX 0
34 #define mmHDP_NONSURFACE_INFO 0x0041
35 #define mmHDP_NONSURFACE_INFO_BASE_IDX 0
36 #define mmHDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_6_0_0_offset.h29 // base address: 0x3c80
30 …HDP_NONSURFACE_BASE 0x0040
31 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
32 …HDP_NONSURFACE_INFO 0x0041
33 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
34 …HDP_NONSURFACE_BASE_HI 0x0042
35 …e regHDP_NONSURFACE_BASE_HI_BASE_IDX 0
36 …HDP_SURFACE_WRITE_FLAGS 0x00c4
37 …e regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
38 …HDP_SURFACE_READ_FLAGS 0x00c5
[all …]
/linux/sound/soc/sof/mediatek/mt8195/
H A Dmt8195.h15 #define DSP_REG_BASE 0x10803000
16 #define SCP_CFGREG_BASE 0x10724000
17 #define DSP_SYSAO_BASE 0x1080C000
22 #define DSP_JTAGMUX 0x0000
23 #define DSP_ALTRESETVEC 0x0004
24 #define DSP_PDEBUGDATA 0x0008
25 #define DSP_PDEBUGBUS0 0x000c
26 #define PDEBUG_ENABLE BIT(0)
27 #define DSP_PDEBUGBUS1 0x0010
28 #define DSP_PDEBUGINST 0x0014
[all …]

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