31 #define regATHUB_MISC_CNTL_V3_0_1			0x00d7
32 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX		0
33 #define regATHUB_MISC_CNTL_V3_3_0			0x00d8
34 #define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX		0
41 	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {  in athub_v3_0_get_cg_cntl()
42 	case IP_VERSION(3, 0, 1):  in athub_v3_0_get_cg_cntl()
43 		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);  in athub_v3_0_get_cg_cntl()
45 	case IP_VERSION(3, 3, 0):  in athub_v3_0_get_cg_cntl()
46 		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);  in athub_v3_0_get_cg_cntl()
49 		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);  in athub_v3_0_get_cg_cntl()
57 	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {  in athub_v3_0_set_cg_cntl()
58 	case IP_VERSION(3, 0, 1):  in athub_v3_0_set_cg_cntl()
59 		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);  in athub_v3_0_set_cg_cntl()
61 	case IP_VERSION(3, 3, 0):  in athub_v3_0_set_cg_cntl()
62 		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);  in athub_v3_0_set_cg_cntl()
65 		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);  in athub_v3_0_set_cg_cntl()
108 		return 0;  in athub_v3_0_set_clockgating()
110 	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {  in athub_v3_0_set_clockgating()
111 	case IP_VERSION(3, 0, 0):  in athub_v3_0_set_clockgating()
112 	case IP_VERSION(3, 0, 1):  in athub_v3_0_set_clockgating()
113 	case IP_VERSION(3, 0, 2):  in athub_v3_0_set_clockgating()
114 	case IP_VERSION(3, 3, 0):  in athub_v3_0_set_clockgating()
124 	return 0;  in athub_v3_0_set_clockgating()