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/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.c24 #define B2055_INITTAB_ENTRY_OK 0x01
25 #define B2055_INITTAB_UPLOAD 0x02
31 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
32 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
33 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
34 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
35 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
36 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
37 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
38 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
H A Dradio_2056.c24 #define B2056_INITTAB_ENTRY_OK 0x01
25 #define B2056_INITTAB_UPLOAD 0x02
39 [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
40 [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
41 [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
42 [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
43 [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
44 [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
45 [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
46 [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_2_3_offset.h27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/arch/arm/mach-mmp/
H A Dregs-timers.h9 #define TMR_CCR (0x0000)
10 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
11 #define TMR_CR(n) (0x0028 + ((n) << 2))
12 #define TMR_SR(n) (0x0034 + ((n) << 2))
13 #define TMR_IER(n) (0x0040 + ((n) << 2))
14 #define TMR_PLVR(n) (0x004c + ((n) << 2))
15 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
16 #define TMR_WMER (0x0064)
17 #define TMR_WMR (0x0068)
18 #define TMR_WVR (0x006c)
[all …]
/linux/sound/pci/ymfpci/
H A Dymfpci.h22 #define YDSXGR_INTFLAG 0x0004
23 #define YDSXGR_ACTIVITY 0x0006
24 #define YDSXGR_GLOBALCTRL 0x0008
25 #define YDSXGR_ZVCTRL 0x000A
26 #define YDSXGR_TIMERCTRL 0x0010
27 #define YDSXGR_TIMERCOUNT 0x0012
28 #define YDSXGR_SPDIFOUTCTRL 0x0018
29 #define YDSXGR_SPDIFOUTSTATUS 0x001C
30 #define YDSXGR_EEPROMCTRL 0x0020
31 #define YDSXGR_SPDIFINCTRL 0x0034
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-trekstor.c15 { 0x0084, KEY_NUMERIC_0 },
16 { 0x0085, KEY_MUTE }, /* Mute */
17 { 0x0086, KEY_HOMEPAGE }, /* Home */
18 { 0x0087, KEY_UP }, /* Up */
19 { 0x0088, KEY_OK }, /* OK */
20 { 0x0089, KEY_RIGHT }, /* Right */
21 { 0x008a, KEY_FASTFORWARD }, /* Fast forward */
22 { 0x008b, KEY_VOLUMEUP }, /* Volume + */
23 { 0x008c, KEY_DOWN }, /* Down */
24 { 0x008d, KEY_PLAY }, /* Play/Pause */
[all …]
/linux/arch/s390/kernel/
H A Dperf_cpum_cf_events.c14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_2_offset.h28 // base address: 0x0
29 …MP1_SMN_C2PMSG_0 0x0040
31 …MP1_SMN_C2PMSG_1 0x0041
33 …MP1_SMN_C2PMSG_2 0x0042
35 …MP1_SMN_C2PMSG_3 0x0043
37 …MP1_SMN_C2PMSG_4 0x0044
39 …MP1_SMN_C2PMSG_5 0x0045
41 …MP1_SMN_C2PMSG_6 0x0046
43 …MP1_SMN_C2PMSG_7 0x0047
45 …MP1_SMN_C2PMSG_8 0x0048
[all …]
/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux/drivers/net/fjes/
H A Dfjes_regs.h12 #define XSCT_DEVICE_REGISTER_SIZE 0x1000
16 #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */
17 #define XSCT_MAX_EP 0x0004 /* Maximum EP */
20 #define XSCT_DCTL 0x0010 /* Device Control */
23 #define XSCT_CR 0x0020 /* Command request */
24 #define XSCT_CS 0x0024 /* Command status */
25 #define XSCT_SHSTSAL 0x0028 /* Share status address Low */
26 #define XSCT_SHSTSAH 0x002C /* Share status address High */
28 #define XSCT_REQBL 0x0034 /* Request Buffer length */
29 #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
H A Dgt200.c33 .mthd = 0x0000,
34 .addr = 0x000000,
36 { 0x0080, 0x000000 },
37 { 0x0084, 0x6109a0 },
38 { 0x0088, 0x6109c0 },
39 { 0x008c, 0x6109c8 },
40 { 0x0090, 0x6109b4 },
41 { 0x0094, 0x610970 },
42 { 0x00a0, 0x610998 },
43 { 0x00a4, 0x610964 },
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-regs.h20 #define HDMA_V0_STOP_INT_MASK BIT(0)
21 #define HDMA_V0_LINKLIST_EN BIT(0)
23 #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0)
24 #define HDMA_V0_DOORBELL_START BIT(0)
25 #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)
28 u32 ch_en; /* 0x0000 */
29 u32 doorbell; /* 0x0004 */
30 u32 prefetch; /* 0x0008 */
31 u32 handshake; /* 0x000c */
33 u64 reg; /* 0x0010..0x0014 */
[all …]
/linux/Documentation/arch/arm/
H A Dnetwinder.rst15 0x0000 0x000f DMA1
16 0x0020 0x0021 PIC1
17 0x0060 0x006f Keyboard
18 0x0070 0x007f RTC
19 0x0080 0x0087 DMA1
20 0x0088 0x008f DMA2
21 0x00a0 0x00a3 PIC2
22 0x00c0 0x00df DMA2
23 0x0180 0x0187 IRDA
24 0x01f0 0x01f6 ide0
[all …]

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