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12 #define XSCT_DEVICE_REGISTER_SIZE 0x1000
16 #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */
17 #define XSCT_MAX_EP 0x0004 /* Maximum EP */
20 #define XSCT_DCTL 0x0010 /* Device Control */
23 #define XSCT_CR 0x0020 /* Command request */
24 #define XSCT_CS 0x0024 /* Command status */
25 #define XSCT_SHSTSAL 0x0028 /* Share status address Low */
26 #define XSCT_SHSTSAH 0x002C /* Share status address High */
28 #define XSCT_REQBL 0x0034 /* Request Buffer length */
29 #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
30 #define XSCT_REQBAH 0x003C /* Request Buffer Address High */
32 #define XSCT_RESPBL 0x0044 /* Response Buffer Length */
33 #define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */
34 #define XSCT_RESPBAH 0x004C /* Response Buffer Address High */
37 #define XSCT_IS 0x0080 /* Interrupt status */
38 #define XSCT_IMS 0x0084 /* Interrupt mask set */
39 #define XSCT_IMC 0x0088 /* Interrupt mask clear */
40 #define XSCT_IG 0x008C /* Interrupt generator */
41 #define XSCT_ICTL 0x0090 /* Interrupt control */
112 REG_IS_MASK_EPID = GENMASK(15, 0),
123 } while (0)