Lines Matching +full:0 +full:x0088
33 .mthd = 0x0000,
34 .addr = 0x000000,
36 { 0x0080, 0x000000 },
37 { 0x0084, 0x6109a0 },
38 { 0x0088, 0x6109c0 },
39 { 0x008c, 0x6109c8 },
40 { 0x0090, 0x6109b4 },
41 { 0x0094, 0x610970 },
42 { 0x00a0, 0x610998 },
43 { 0x00a4, 0x610964 },
44 { 0x00b0, 0x610c98 },
45 { 0x00b4, 0x610ca4 },
46 { 0x00b8, 0x610cac },
47 { 0x00c0, 0x610958 },
48 { 0x00e0, 0x6109a8 },
49 { 0x00e4, 0x6109d0 },
50 { 0x00e8, 0x6109d8 },
51 { 0x0100, 0x61094c },
52 { 0x0104, 0x610984 },
53 { 0x0108, 0x61098c },
54 { 0x0800, 0x6109f8 },
55 { 0x0808, 0x610a08 },
56 { 0x080c, 0x610a10 },
57 { 0x0810, 0x610a00 },
65 .addr = 0x000540,
66 .prev = 0x000004,
93 .root = { 0,0,GT200_DISP },
95 {{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },
96 {{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },
97 {{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },
98 {{0,0,GT200_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g84_disp_core },
99 {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, >200_disp_ovly },