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/linux/arch/arm/mach-omap2/
H A Dprm2xxx.h35 #define OMAP2_PRCM_REVISION_OFFSET 0x0000
36 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
37 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
38 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
40 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
41 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
42 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
43 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
45 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
46 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi30 pinctrl-0 = <&d0_uart0_rxd>;
85 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
92 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7)
99 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7)
106 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7)
113 AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
120 AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
127 AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
134 AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
141 AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_dw_hdmi.c17 #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
18 #define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
19 #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
29 { 35500000, 0x0003, 0x0344, 0x0328 },
30 { 44900000, 0x0003, 0x0285, 0x0128 },
31 { 71000000, 0x0002, 0x1184, 0x0314 },
32 { 90000000, 0x0002, 0x1144, 0x0114 },
33 { 140250000, 0x0001, 0x20c4, 0x030a },
34 { 182750000, 0x0001, 0x2084, 0x010a },
35 { 281250000, 0x0000, 0x0084, 0x0305 },
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/linux/drivers/net/ethernet/engleder/
H A Dtsnep_hw.h12 #define ECM_TYPE 0x0000
13 #define ECM_REVISION_MASK 0x000000FF
14 #define ECM_REVISION_SHIFT 0
15 #define ECM_VERSION_MASK 0x0000FF00
17 #define ECM_QUEUE_COUNT_MASK 0x00070000
19 #define ECM_GATE_CONTROL 0x02000000
22 #define ECM_SYSTEM_TIME_LOW 0x0008
23 #define ECM_SYSTEM_TIME_HIGH 0x000C
26 #define ECM_CLOCK_RATE 0x0010
27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
[all …]
/linux/arch/s390/kernel/
H A Dperf_cpum_cf_events.c14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x08_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
/linux/drivers/net/phy/
H A Dmicrochip_t1s.c14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN867X_REVC1 0x0007C164
16 #define PHY_ID_LAN867X_REVC2 0x0007C165
18 #define PHY_ID_LAN865X_REVB 0x0007C1B3
20 #define LAN867X_REG_STS2 0x0019
24 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
25 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
26 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
27 #define LAN865X_REG_STS2 0x0019
29 /* Collision Detector Control 0 Register */
[all …]
/linux/arch/arm/mach-mmp/
H A Dregs-timers.h9 #define TMR_CCR (0x0000)
10 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
11 #define TMR_CR(n) (0x0028 + ((n) << 2))
12 #define TMR_SR(n) (0x0034 + ((n) << 2))
13 #define TMR_IER(n) (0x0040 + ((n) << 2))
14 #define TMR_PLVR(n) (0x004c + ((n) << 2))
15 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
16 #define TMR_WMER (0x0064)
17 #define TMR_WMR (0x0068)
18 #define TMR_WVR (0x006c)
[all …]
/linux/sound/pci/ymfpci/
H A Dymfpci.h22 #define YDSXGR_INTFLAG 0x0004
23 #define YDSXGR_ACTIVITY 0x0006
24 #define YDSXGR_GLOBALCTRL 0x0008
25 #define YDSXGR_ZVCTRL 0x000A
26 #define YDSXGR_TIMERCTRL 0x0010
27 #define YDSXGR_TIMERCOUNT 0x0012
28 #define YDSXGR_SPDIFOUTCTRL 0x0018
29 #define YDSXGR_SPDIFOUTSTATUS 0x001C
30 #define YDSXGR_EEPROMCTRL 0x0020
31 #define YDSXGR_SPDIFINCTRL 0x0034
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-trekstor.c15 { 0x0084, KEY_NUMERIC_0 },
16 { 0x0085, KEY_MUTE }, /* Mute */
17 { 0x0086, KEY_HOMEPAGE }, /* Home */
18 { 0x0087, KEY_UP }, /* Up */
19 { 0x0088, KEY_OK }, /* OK */
20 { 0x0089, KEY_RIGHT }, /* Right */
21 { 0x008a, KEY_FASTFORWARD }, /* Fast forward */
22 { 0x008b, KEY_VOLUMEUP }, /* Volume + */
23 { 0x008c, KEY_DOWN }, /* Down */
24 { 0x008d, KEY_PLAY }, /* Play/Pause */
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_2_offset.h28 // base address: 0x0
29 …MP1_SMN_C2PMSG_0 0x0040
31 …MP1_SMN_C2PMSG_1 0x0041
33 …MP1_SMN_C2PMSG_2 0x0042
35 …MP1_SMN_C2PMSG_3 0x0043
37 …MP1_SMN_C2PMSG_4 0x0044
39 …MP1_SMN_C2PMSG_5 0x0045
41 …MP1_SMN_C2PMSG_6 0x0046
43 …MP1_SMN_C2PMSG_7 0x0047
45 …MP1_SMN_C2PMSG_8 0x0048
[all …]
/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/linux/include/rdma/
H A Dopa_smi.h20 #define OPA_LID_PERMISSIVE cpu_to_be32(0xFFFFFFFF)
53 #define OPA_ATTRIB_ID_NODE_DESCRIPTION cpu_to_be16(0x0010)
54 #define OPA_ATTRIB_ID_NODE_INFO cpu_to_be16(0x0011)
55 #define OPA_ATTRIB_ID_PORT_INFO cpu_to_be16(0x0015)
56 #define OPA_ATTRIB_ID_PARTITION_TABLE cpu_to_be16(0x0016)
57 #define OPA_ATTRIB_ID_SL_TO_SC_MAP cpu_to_be16(0x0017)
58 #define OPA_ATTRIB_ID_VL_ARBITRATION cpu_to_be16(0x0018)
59 #define OPA_ATTRIB_ID_SM_INFO cpu_to_be16(0x0020)
60 #define OPA_ATTRIB_ID_CABLE_INFO cpu_to_be16(0x0032)
61 #define OPA_ATTRIB_ID_AGGREGATE cpu_to_be16(0x0080)
[all …]
/linux/drivers/net/fjes/
H A Dfjes_regs.h12 #define XSCT_DEVICE_REGISTER_SIZE 0x1000
16 #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */
17 #define XSCT_MAX_EP 0x0004 /* Maximum EP */
20 #define XSCT_DCTL 0x0010 /* Device Control */
23 #define XSCT_CR 0x0020 /* Command request */
24 #define XSCT_CS 0x0024 /* Command status */
25 #define XSCT_SHSTSAL 0x0028 /* Share status address Low */
26 #define XSCT_SHSTSAH 0x002C /* Share status address High */
28 #define XSCT_REQBL 0x0034 /* Request Buffer length */
29 #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
H A Dgt200.c33 .mthd = 0x0000,
34 .addr = 0x000000,
36 { 0x0080, 0x000000 },
37 { 0x0084, 0x6109a0 },
38 { 0x0088, 0x6109c0 },
39 { 0x008c, 0x6109c8 },
40 { 0x0090, 0x6109b4 },
41 { 0x0094, 0x610970 },
42 { 0x00a0, 0x610998 },
43 { 0x00a4, 0x610964 },
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-regs.h20 #define HDMA_V0_STOP_INT_MASK BIT(0)
21 #define HDMA_V0_LINKLIST_EN BIT(0)
23 #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0)
24 #define HDMA_V0_DOORBELL_START BIT(0)
25 #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)
28 u32 ch_en; /* 0x0000 */
29 u32 doorbell; /* 0x0004 */
30 u32 prefetch; /* 0x0008 */
31 u32 handshake; /* 0x000c */
33 u64 reg; /* 0x0010..0x0014 */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]

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