37 	const u32 hoff = head * 0x800;  in g84_sor_hdmi_infoframe_vsi()
39 	nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000);  in g84_sor_hdmi_infoframe_vsi()
45 	nvkm_wr32(device, 0x616544 + hoff, vsi.header);  in g84_sor_hdmi_infoframe_vsi()
46 	nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low);  in g84_sor_hdmi_infoframe_vsi()
47 	nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high);  in g84_sor_hdmi_infoframe_vsi()
49 	/* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */  in g84_sor_hdmi_infoframe_vsi()
50 	/* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */  in g84_sor_hdmi_infoframe_vsi()
52 	nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001);  in g84_sor_hdmi_infoframe_vsi()
60 	const u32 hoff = head * 0x800;  in g84_sor_hdmi_infoframe_avi()
64 	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);  in g84_sor_hdmi_infoframe_avi()
68 	nvkm_wr32(device, 0x616528 + hoff, avi.header);  in g84_sor_hdmi_infoframe_avi()
69 	nvkm_wr32(device, 0x61652c + hoff, avi.subpack0_low);  in g84_sor_hdmi_infoframe_avi()
70 	nvkm_wr32(device, 0x616530 + hoff, avi.subpack0_high);  in g84_sor_hdmi_infoframe_avi()
71 	nvkm_wr32(device, 0x616534 + hoff, avi.subpack1_low);  in g84_sor_hdmi_infoframe_avi()
72 	nvkm_wr32(device, 0x616538 + hoff, avi.subpack1_high);  in g84_sor_hdmi_infoframe_avi()
74 	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);  in g84_sor_hdmi_infoframe_avi()
82 	const u32 ctrl = 0x40000000 * enable |  in g84_sor_hdmi_ctrl()
83 			 0x1f000000 /* ??? */ |  in g84_sor_hdmi_ctrl()
86 	const u32 hoff = head * 0x800;  in g84_sor_hdmi_ctrl()
88 	if (!(ctrl & 0x40000000)) {  in g84_sor_hdmi_ctrl()
89 		nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);  in g84_sor_hdmi_ctrl()
90 		nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);  in g84_sor_hdmi_ctrl()
95 	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);  in g84_sor_hdmi_ctrl()
96 	nvkm_wr32(device, 0x616508 + hoff, 0x000a0184);  in g84_sor_hdmi_ctrl()
97 	nvkm_wr32(device, 0x61650c + hoff, 0x00000071);  in g84_sor_hdmi_ctrl()
98 	nvkm_wr32(device, 0x616510 + hoff, 0x00000000);  in g84_sor_hdmi_ctrl()
99 	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);  in g84_sor_hdmi_ctrl()
102 	nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */  in g84_sor_hdmi_ctrl()
103 	nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */  in g84_sor_hdmi_ctrl()
104 	nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */  in g84_sor_hdmi_ctrl()
107 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */  in g84_sor_hdmi_ctrl()
108 	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */  in g84_sor_hdmi_ctrl()
109 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */  in g84_sor_hdmi_ctrl()
112 	nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);  in g84_sor_hdmi_ctrl()
139 	.mthd = 0x0000,
140 	.addr = 0x000000,
142 		{ 0x0080, 0x000000 },
143 		{ 0x0084, 0x6109a0 },
144 		{ 0x0088, 0x6109c0 },
145 		{ 0x008c, 0x6109c8 },
146 		{ 0x0090, 0x6109b4 },
147 		{ 0x0094, 0x610970 },
148 		{ 0x00a0, 0x610998 },
149 		{ 0x00a4, 0x610964 },
150 		{ 0x00c0, 0x610958 },
151 		{ 0x00e0, 0x6109a8 },
152 		{ 0x00e4, 0x6109d0 },
153 		{ 0x00e8, 0x6109d8 },
154 		{ 0x0100, 0x61094c },
155 		{ 0x0104, 0x610984 },
156 		{ 0x0108, 0x61098c },
157 		{ 0x0800, 0x6109f8 },
158 		{ 0x0808, 0x610a08 },
159 		{ 0x080c, 0x610a10 },
160 		{ 0x0810, 0x610a00 },
168 	.addr = 0x000540,
169 	.prev = 0x000004,
186 	.mthd = 0x0000,
187 	.addr = 0x000000,
189 		{ 0x0080, 0x000000 },
190 		{ 0x0084, 0x0008c4 },
191 		{ 0x0088, 0x0008d0 },
192 		{ 0x008c, 0x0008dc },
193 		{ 0x0090, 0x0008e4 },
194 		{ 0x0094, 0x610884 },
195 		{ 0x00a0, 0x6108a0 },
196 		{ 0x00a4, 0x610878 },
197 		{ 0x00c0, 0x61086c },
198 		{ 0x00c4, 0x610800 },
199 		{ 0x00c8, 0x61080c },
200 		{ 0x00cc, 0x610818 },
201 		{ 0x00e0, 0x610858 },
202 		{ 0x00e4, 0x610860 },
203 		{ 0x00e8, 0x6108ac },
204 		{ 0x00ec, 0x6108b4 },
205 		{ 0x00fc, 0x610824 },
206 		{ 0x0100, 0x610894 },
207 		{ 0x0104, 0x61082c },
208 		{ 0x0110, 0x6108bc },
209 		{ 0x0114, 0x61088c },
217 	.addr = 0x000540,
218 	.prev = 0x000004,
236 	.mthd = 0x0080,
237 	.addr = 0x000008,
239 		{ 0x0400, 0x610b58 },
240 		{ 0x0404, 0x610bdc },
241 		{ 0x0420, 0x610bc4 },
248 	.mthd = 0x0400,
249 	.addr = 0x000540,
251 		{ 0x0800, 0x610ad8 },
252 		{ 0x0804, 0x610ad0 },
253 		{ 0x0808, 0x610a48 },
254 		{ 0x080c, 0x610a78 },
255 		{ 0x0810, 0x610ac0 },
256 		{ 0x0814, 0x610af8 },
257 		{ 0x0818, 0x610b00 },
258 		{ 0x081c, 0x610ae8 },
259 		{ 0x0820, 0x610af0 },
260 		{ 0x0824, 0x610b08 },
261 		{ 0x0828, 0x610b10 },
262 		{ 0x082c, 0x610a68 },
263 		{ 0x0830, 0x610a60 },
264 		{ 0x0834, 0x000000 },
265 		{ 0x0838, 0x610a40 },
266 		{ 0x0840, 0x610a24 },
267 		{ 0x0844, 0x610a2c },
268 		{ 0x0848, 0x610aa8 },
269 		{ 0x084c, 0x610ab0 },
270 		{ 0x085c, 0x610c5c },
271 		{ 0x0860, 0x610a84 },
272 		{ 0x0864, 0x610a90 },
273 		{ 0x0868, 0x610b18 },
274 		{ 0x086c, 0x610b20 },
275 		{ 0x0870, 0x610ac8 },
276 		{ 0x0874, 0x610a38 },
277 		{ 0x0878, 0x610c50 },
278 		{ 0x0880, 0x610a58 },
279 		{ 0x0884, 0x610a9c },
280 		{ 0x089c, 0x610c68 },
281 		{ 0x08a0, 0x610a70 },
282 		{ 0x08a4, 0x610a50 },
283 		{ 0x08a8, 0x610ae0 },
284 		{ 0x08c0, 0x610b28 },
285 		{ 0x08c4, 0x610b30 },
286 		{ 0x08c8, 0x610b40 },
287 		{ 0x08d4, 0x610b38 },
288 		{ 0x08d8, 0x610b48 },
289 		{ 0x08dc, 0x610b50 },
290 		{ 0x0900, 0x610a18 },
291 		{ 0x0904, 0x610ab8 },
292 		{ 0x0910, 0x610c70 },
293 		{ 0x0914, 0x610c78 },
301 	.addr = 0x000000,
302 	.prev = 0x000004,
316 	.ctrl = 0,
317 	.user = 0,
333 	.root = { 0,0,G82_DISP },
335 		{{0,0,G82_DISP_CURSOR             }, nvkm_disp_chan_new, &nv50_disp_curs },
336 		{{0,0,G82_DISP_OVERLAY            }, nvkm_disp_chan_new, &nv50_disp_oimm },
337 		{{0,0,G82_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, & g84_disp_base },
338 		{{0,0,G82_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, & g84_disp_core },
339 		{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },