Home
last modified time | relevance | path

Searched +full:0 +full:x00800000 (Results 1 – 25 of 453) sorted by relevance

12345678910>>...19

/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/arch/sh/kernel/cpu/sh2a/
H A Dfpu.c21 #define FPSCR_RCHG 0x00000000
32 asm volatile("sts.l fpul, @-%0\n\t" in save_fpu()
33 "sts.l fpscr, @-%0\n\t" in save_fpu()
34 "fmov.s fr15, @-%0\n\t" in save_fpu()
35 "fmov.s fr14, @-%0\n\t" in save_fpu()
36 "fmov.s fr13, @-%0\n\t" in save_fpu()
37 "fmov.s fr12, @-%0\n\t" in save_fpu()
38 "fmov.s fr11, @-%0\n\t" in save_fpu()
39 "fmov.s fr10, @-%0\n\t" in save_fpu()
40 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/linux/drivers/mfd/
H A Dcs42l43.c42 #define CS42L43_MCU_UPDATE_OFFSET 0x100000
46 #define CS42L43_MCU_ROM_REV 0x2001
47 #define CS42L43_MCU_ROM_BIOS_REV 0x0000
49 #define CS42L43_MCU_SUPPORTED_REV 0x2105
50 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
51 #define CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV 0x1002
52 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
76 { 0x4000, 0x00000055 },
77 { 0x4000, 0x000000AA },
78 { 0x10084, 0x00000000 },
[all …]
/linux/arch/powerpc/boot/dts/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dfpu.c22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
54 "fmov.s fr11, @-%0\n\t" in save_fpu()
55 "fmov.s fr10, @-%0\n\t" in save_fpu()
56 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9340_initvals.h37 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
38 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
39 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
40 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
41 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
46 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
47 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
48 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
49 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
50 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
[all …]
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/sound/drivers/vx/
H A Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/linux/arch/arm/
H A DKconfig-nommu15 default 0x00800000
19 default 0x00800000
24 default 0x00400000
29 default 0x00400000
33 default 0x00007700
44 placed at address 0x00000000. However, this region may be
/linux/include/soc/fsl/qe/
H A Ducc_slow.h22 #define T_R 0x80000000 /* ready bit */
23 #define T_PAD 0x40000000 /* add pads to short frames */
24 #define T_W 0x20000000 /* wrap bit */
25 #define T_I 0x10000000 /* interrupt on completion */
26 #define T_L 0x08000000 /* last */
28 #define T_A 0x04000000 /* Address - the data transmitted as address
30 #define T_TC 0x04000000 /* transmit CRC */
31 #define T_CM 0x02000000 /* continuous mode */
32 #define T_DEF 0x02000000 /* collision on previous attempt to transmit */
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Ddesc.h25 * @rx_control_0: RX control word 0
34 #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
35 #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
39 * @rx_status_0: RX status word 0
50 /* RX status word 0 fields/flags */
51 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */
52 #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */
53 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000 /* [5210] receive on ant 1 */
54 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 /* reception rate */
56 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 /* rssi */
[all …]
/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
/linux/arch/arm/boot/bootp/
H A DMakefile10 add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
19 PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
22 initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
23 initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
24 initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
/linux/arch/mips/math-emu/
H A Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso38 reg = <0x00 0x02900000 0x00 0x1000>,
39 <0x00 0x02907000 0x00 0x400>,
40 <0x00 0x0d000000 0x00 0x00800000>,
41 <0x00 0x10000000 0x00 0x08000000>;
45 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
49 clocks = <&k3_clks 332 0>;
52 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
60 reg = <0x00 0x02910000 0x00 0x1000>,
61 <0x00 0x02917000 0x00 0x400>,
62 <0x00 0x0d800000 0x00 0x00800000>,
[all …]
/linux/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h18 #define PORT_CPM 0
24 #define USB_MAX_CTRL_PAYLOAD 0x4000
31 #define USB_DIR_BOTH 0x88
32 #define R_BUF_MAXSIZE 0x800
36 #define USB_MODE_EN 0x01
37 #define USB_MODE_HOST 0x02
38 #define USB_MODE_TEST 0x04
39 #define USB_MODE_SFTE 0x08
40 #define USB_MODE_RESUME 0x40
41 #define USB_MODE_LSS 0x80
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dppa8548.dts22 reg = <0 0 0x0 0x40000000>;
26 reg = <0xf 0xe0005000 0 0x1000>;
27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
31 ranges = <0 0xf 0xe0000000 0x100000>;
50 reg = <0xf 0xe00c0000 0x0 0x11000>;
52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
58 nor@0 {
62 reg = <0x0 0x0 0x00800000>;
66 partition@0 {
67 reg = <0x0 0x7A0000>;
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927.h36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
[all …]
/linux/drivers/net/ethernet/ibm/emac/
H A Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
H A Demac.h103 #define EMAC_MR0_RXI 0x80000000
104 #define EMAC_MR0_TXI 0x40000000
105 #define EMAC_MR0_SRST 0x20000000
106 #define EMAC_MR0_TXE 0x10000000
107 #define EMAC_MR0_RXE 0x08000000
108 #define EMAC_MR0_WKE 0x04000000
111 #define EMAC_MR1_FDE 0x80000000
112 #define EMAC_MR1_ILE 0x40000000
113 #define EMAC_MR1_VLE 0x20000000
114 #define EMAC_MR1_EIFC 0x10000000
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]

12345678910>>...19