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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx27-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
35 #define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
36 #define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
[all …]
H A Dimx1-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX1_PAD_A24__A24 0x00 0x004
35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032
36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006
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/freebsd/sys/dev/sound/pci/
H A Dcs4281.h32 #define CS4281_PCI_ID 0x60051013
39 #define CS4281PCI_HISR 0x000
40 # define CS4281PCI_HISR_DMAI 0x00040000
41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x))
43 #define CS4281PCI_HICR 0x008
44 # define CS4281PCI_HICR_EOI 0x00000003
46 #define CS4281PCI_HIMR 0x00c
47 # define CS4281PCI_HIMR_DMAI 0x00040000
48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x))
50 #define CS4281PCI_IIER 0x010
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/freebsd/sys/dev/hyperv/netvsc/
H A Dndis.h30 #define NDIS_MEDIA_STATE_CONNECTED 0
37 #define NDIS_OFFLOAD_SET_NOCHG 0
42 #define NDIS_ENCAP_TYPE_NVGRE 0x00000001
44 #define NDIS_HASH_FUNCTION_MASK 0x000000FF /* see hash function */
45 #define NDIS_HASH_TYPE_MASK 0x00FFFF00 /* see hash type */
48 #define NDIS_HASH_FUNCTION_TOEPLITZ 0x00000001
51 #define NDIS_HASH_IPV4 0x00000100
52 #define NDIS_HASH_TCP_IPV4 0x00000200
53 #define NDIS_HASH_IPV6 0x00000400
54 #define NDIS_HASH_IPV6_EX 0x00000800
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_mcp.h41 #define DPAA2_MCP_MEM_WIDTH 0x40 /* Minimal size of the MC portal. */
49 #define DPAA2_PORTAL_DEF 0x0u
50 #define DPAA2_PORTAL_NOWAIT_ALLOC 0x2u /* Do not sleep during init */
51 #define DPAA2_PORTAL_LOCKED 0x4000u /* Wait till portal's unlocked */
52 #define DPAA2_PORTAL_DESTROYED 0x8000u /* Terminate any operations */
55 #define DPAA2_CMD_DEF 0x0u
56 #define DPAA2_CMD_HIGH_PRIO 0x80u /* High priority command */
57 #define DPAA2_CMD_INTR_DIS 0x100u /* Disable cmd finished intr */
58 #define DPAA2_CMD_NOWAIT_ALLOC 0x8000u /* Do not sleep during init */
61 #define DPAA2_CMD_STAT_OK 0x0 /* Set by MC on success */
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/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq6h-pins.dtsi9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
27 0x000 0x200 // I2C0_SCL pin
28 0x004 0x200 // I2C0_SDA pin
33 0x008 0x200 // I2C1_SCL pin
34 0x00c 0x200 // I2C1_SDA pin
39 0x080 1 // GPIO_C4__SMA0_MDC pin
40 0x084 1 // GPIO_C5__SMA0_MDIO pin
44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
14 number on the specific port (between 0 and 31).
21 0 - Primary function
28 0 - Input
37 0 - A_IN
46 0 - GPIO_IN
52 CONFIG can be 0 or 1, meaning Pullup disable/enable.
64 reg = <0x10015000 0x600>;
78 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
79 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
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/freebsd/contrib/nvi/common/
H A Dexf.h49 #define F_DEVSET 0x001 /* mdev/minode fields initialized. */
50 #define F_FIRSTMODIFY 0x002 /* File not yet modified. */
51 #define F_MODIFIED 0x004 /* File is currently dirty. */
52 #define F_MULTILOCK 0x008 /* Multiple processes running, lock. */
53 #define F_NOLOG 0x010 /* Logging turned off. */
54 #define F_RCV_NORM 0x020 /* Don't delete recovery files. */
55 #define F_RCV_ON 0x040 /* Recovery is possible. */
56 #define F_UNDO 0x080 /* No change since last undo. */
61 #define DBG_FATAL 0x001 /* If DNE, error message. */
62 #define DBG_NOCACHE 0x002 /* Ignore the front-end cache. */
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/freebsd/sys/dev/hwpmc/
H A Dpmu_dmc620_reg.h35 #define DMC620_SNAPSHOT_REQ 0x000 /* WO */
36 #define DMC620_SNAPSHOT_ACK 0x004 /* RO */
37 #define DMC620_OVERFLOW_STATUS_CLKDIV2 0x008 /* RW */
38 #define DMC620_OVERFLOW_STATUS_CLK 0x00C /* RW */
40 #define DMC620_COUNTER_MASK_LO 0x000 /* RW */
41 #define DMC620_COUNTER_MASK_HI 0x004 /* RW */
42 #define DMC620_COUNTER_MATCH_LO 0x008 /* RW */
43 #define DMC620_COUNTER_MATCH_HI 0x00C /* RW */
44 #define DMC620_COUNTER_CONTROL 0x010 /* RW */
45 #define DMC620_COUNTER_CONTROL_ENABLE (1 << 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey960-pinctrl.dtsi18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
[all …]
H A Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/freebsd/sys/amd64/include/
H A Dpte.h51 #define X86_PG_V 0x001 /* P Valid */
52 #define X86_PG_RW 0x002 /* R/W Read/Write */
53 #define X86_PG_U 0x004 /* U/S User/Supervisor */
54 #define X86_PG_NC_PWT 0x008 /* PWT Write through */
55 #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
56 #define X86_PG_A 0x020 /* A Accessed */
57 #define X86_PG_M 0x040 /* D Dirty */
58 #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
59 #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
60 #define X86_PG_G 0x100 /* G Global */
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
25 { "PIDX", 0, 13 },
26 { "SGE_VF_GTS", 0x004, 0 },
30 { "CIDXInc", 0, 12 },
32 { NULL, 0, 0 }
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x
[all...]
H A Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dwcs.h33 0x011, // 00000 = 0 - PHY_RESET_START
34 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY
35 0x009, // 0x002 = 2 -
36 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE
37 0x010, // 0x004 = 4 -
38 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED
39 0x01e, // 0x006 = 6 -
40 0x0ff, // 0x007 = 7 - JUMP
41 0x001, // 0x008 = 8 -
42 0x010, // 0x009 = 9 - SEND_ID_FRAME
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Deeprom.h12 MT_EE_CHIP_ID = 0x000,
13 MT_EE_VERSION = 0x002,
14 MT_EE_MAC_ADDR = 0x004,
15 MT_EE_MAC_ADDR2 = 0x00a,
16 MT_EE_WIFI_CONF = 0x190,
17 MT_EE_MAC_ADDR3 = 0x2c0,
18 MT_EE_RATE_DELTA_2G = 0x1400,
19 MT_EE_RATE_DELTA_5G = 0x147d,
20 MT_EE_RATE_DELTA_6G = 0x154a,
21 MT_EE_TX0_POWER_2G = 0x1300,
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbaikal,bt1-l2-ctl.yaml30 default: 0
31 minimum: 0
37 default: 0
38 minimum: 0
45 minimum: 0
57 reg = <0x1f04d028 0x004>;
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml30 default: 0
31 minimum: 0
37 default: 0
38 minimum: 0
45 minimum: 0
57 reg = <0x1f04d028 0x004>;
/freebsd/sys/compat/linux/
H A Dlinux_event.h30 #define LINUX_EPOLLIN 0x001
31 #define LINUX_EPOLLPRI 0x002
32 #define LINUX_EPOLLOUT 0x004
33 #define LINUX_EPOLLRDNORM 0x040
34 #define LINUX_EPOLLRDBAND 0x080
35 #define LINUX_EPOLLWRNORM 0x100
36 #define LINUX_EPOLLWRBAND 0x200
37 #define LINUX_EPOLLMSG 0x400
38 #define LINUX_EPOLLERR 0x008
39 #define LINUX_EPOLLHUP 0x010
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Deeprom.h25 MT_EE_CHIP_ID = 0x000,
26 MT_EE_VERSION = 0x002,
27 MT_EE_MAC_ADDR = 0x004,
28 MT_EE_NIC_CONF_0 = 0x034,
29 MT_EE_NIC_CONF_1 = 0x036,
30 MT_EE_WIFI_CONF = 0x03e,
31 MT_EE_CALDATA_FLASH = 0x052,
32 MT_EE_TX0_2G_TARGET_POWER = 0x058,
33 MT_EE_TX0_5G_G0_TARGET_POWER = 0x070,
34 MT7663_EE_5G_RATE_POWER = 0x089,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dregs.h9 #define MT_MDP_BASE 0x820cd000
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
61 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
63 #define MT_INFRA_CFG_BASE 0xfe000
66 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c)
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]

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