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12

/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dpci.c14 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
57 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
62 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
103 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
104 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7925_reg_addr()
105 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7925_reg_addr()
106 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */ in __mt7925_reg_addr()
107 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */ in __mt7925_reg_addr()
108 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7925_reg_addr()
[all …]
/linux/drivers/net/dsa/ocelot/
H A Dseville_vsc9953.c43 REG(ANA_ADVLEARN, 0x00b500),
44 REG(ANA_VLANMASK, 0x00b504),
46 REG(ANA_ANAGEFIL, 0x00b50c),
47 REG(ANA_ANEVENTS, 0x00b510),
48 REG(ANA_STORMLIMIT_BURST, 0x00b514),
49 REG(ANA_STORMLIMIT_CFG, 0x00b518),
50 REG(ANA_ISOLATED_PORTS, 0x00b528),
51 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
52 REG(ANA_AUTOAGE, 0x00b530),
53 REG(ANA_MACTOPTIONS, 0x00b534),
[all …]
H A Dfelix_vsc9959.c31 #define VSC9959_IMDIO_PCI_BAR 0
49 REG(ANA_ADVLEARN, 0x0089a0),
50 REG(ANA_VLANMASK, 0x0089a4),
52 REG(ANA_ANAGEFIL, 0x0089ac),
53 REG(ANA_ANEVENTS, 0x0089b0),
54 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
55 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
56 REG(ANA_ISOLATED_PORTS, 0x0089c8),
57 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
58 REG(ANA_AUTOAGE, 0x0089d0),
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dinstructions.json4 "EventCode": "0x0000100",
9 "EventCode": "0x0000200",
14 "EventCode": "0x0000400",
19 "EventCode": "0x0000800",
24 "EventCode": "0x0001000",
29 "EventCode": "0x0002000",
34 "EventCode": "0x0004000",
39 "EventCode": "0x0008000",
44 "EventCode": "0x0010000",
49 "EventCode": "0x0020000",
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
[all …]
H A Dcpu-capacity.txt70 #size-cells = <0>;
101 CPU_SLEEP_0: cpu-sleep-0 {
103 arm,psci-suspend-param = <0x0010000>;
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
112 arm,psci-suspend-param = <0x1010000>;
120 A57_0: cpu@0 {
122 reg = <0x0 0x0>;
126 clocks = <&scpi_dvfs 0>;
133 reg = <0x0 0x1>;
137 clocks = <&scpi_dvfs 0>;
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm-common.dtsi90 #size-cells = <0>;
123 <&dra7_pmx_core 0x3e0>;
138 flash@0 {
141 reg = <0>;
152 partition@0 {
154 reg = <0x00000000 0x00010000>;
158 reg = <0x00010000 0x00010000>;
162 reg = <0x00020000 0x00010000>;
166 reg = <0x00030000 0x00010000>;
170 reg = <0x00040000 0x00100000>;
[all …]
H A Dam57xx-idk-common.dtsi64 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
111 hdmi0: connector@0 {
124 tpd12s015: encoder@0 {
127 gpios = <0>, /* optional CT_CP_HPD */
128 <0>, /* optional LS_OE */
133 #size-cells = <0>;
135 port@0 {
136 reg = <0>;
138 tpd12s015_in: endpoint@0 {
146 tpd12s015_out: endpoint@0 {
[all …]
H A Ddra72-evm-common.dtsi129 #size-cells = <0>;
131 port@0 {
132 reg = <0>;
194 #clock-cells = <0>;
202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
221 reg = <0x20>;
230 reg = <0x21>;
[all …]
/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-r1.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A57_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno.dts37 #size-cells = <0>;
68 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 arm,psci-suspend-param = <0x1010000>;
87 A57_0: cpu@0 {
89 reg = <0x0 0x0>;
92 i-cache-size = <0xc000>;
95 d-cache-size = <0x8000>;
99 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno-r2.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A72_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
H A Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101.dtsi34 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0000>;
84 reg = <0x0100>;
94 reg = <0x0200>;
104 reg = <0x0300>;
114 reg = <0x0400>;
124 reg = <0x0500>;
134 reg = <0x0600>;
144 reg = <0x0700>;
[all …]
/linux/include/sound/
H A Dacp63_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x0000000
13 #define ACP_DMA_CNTL_1 0x0000004
14 #define ACP_DMA_CNTL_2 0x0000008
15 #define ACP_DMA_CNTL_3 0x000000C
16 #define ACP_DMA_CNTL_4 0x0000010
17 #define ACP_DMA_CNTL_5 0x0000014
18 #define ACP_DMA_CNTL_6 0x0000018
19 #define ACP_DMA_CNTL_7 0x000001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
/linux/drivers/video/fbdev/
H A Dffb.c64 #define FFB_SFB8R_VOFF 0x00000000
65 #define FFB_SFB8G_VOFF 0x00400000
66 #define FFB_SFB8B_VOFF 0x00800000
67 #define FFB_SFB8X_VOFF 0x00c00000
68 #define FFB_SFB32_VOFF 0x01000000
69 #define FFB_SFB64_VOFF 0x02000000
70 #define FFB_FBC_REGS_VOFF 0x04000000
71 #define FFB_BM_FBC_REGS_VOFF 0x04002000
72 #define FFB_DFB8R_VOFF 0x04004000
73 #define FFB_DFB8G_VOFF 0x04404000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
[all …]

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