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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x67800000 0x00 0x00080000>,
12 <0x00 0x67e00000 0x00 0x0000c000>;
18 ti,sci-proc-ids = <0x33 0xff>;
24 reg = <0x00 0x02920000 0x00 0x1000>,
25 <0x00 0x02927000 0x00 0x400>,
26 <0x00 0x0e000000 0x00 0x00800000>,
27 <0x44 0x00000000 0x00 0x00001000>;
28 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
29 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
37 clocks = <&k3_clks 334 0>;
[all …]
/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dinstructions.json
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml72 default: [0x0001000 0x0002000 0x0004000 0x0008000
73 0x0010000 0x0020000 0x0040000 0x0080000
74 0x0100000 0x0200000 0x0400000 0x0800000
75 0x1000000 0x2000000 0x4000000 0x8000000]
90 reg = <0xffd02000 0x1000>;
91 interrupts = <0 171 4>;
99 reg = <0xffd02000 0x1000>;
100 interrupts = <0 171 4>;
103 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
104 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
[all …]
H A Dcpu-capacity.txt70 #size-cells = <0>;
101 CPU_SLEEP_0: cpu-sleep-0 {
103 arm,psci-suspend-param = <0x0010000>;
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
112 arm,psci-suspend-param = <0x1010000>;
120 A57_0: cpu@0 {
122 reg = <0x0 0x0>;
126 clocks = <&scpi_dvfs 0>;
133 reg = <0x0 0x1>;
137 clocks = <&scpi_dvfs 0>;
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm-common.dtsi90 #size-cells = <0>;
123 <&dra7_pmx_core 0x3e0>;
138 flash@0 {
141 reg = <0>;
152 partition@0 {
154 reg = <0x00000000 0x00010000>;
158 reg = <0x00010000 0x00010000>;
162 reg = <0x00020000 0x00010000>;
166 reg = <0x00030000 0x00010000>;
170 reg = <0x00040000 0x00100000>;
[all …]
H A Dam57xx-idk-common.dtsi64 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
111 hdmi0: connector@0 {
124 tpd12s015: encoder@0 {
127 gpios = <0>, /* optional CT_CP_HPD */
128 <0>, /* optional LS_OE */
133 #size-cells = <0>;
135 port@0 {
136 reg = <0>;
138 tpd12s015_in: endpoint@0 {
146 tpd12s015_out: endpoint@0 {
[all …]
H A Ddra72-evm-common.dtsi129 #size-cells = <0>;
131 port@0 {
132 reg = <0>;
194 #clock-cells = <0>;
202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
221 reg = <0x20>;
230 reg = <0x21>;
[all …]
/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-r1.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A57_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno.dts37 #size-cells = <0>;
68 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 arm,psci-suspend-param = <0x1010000>;
87 A57_0: cpu@0 {
89 reg = <0x0 0x0>;
92 i-cache-size = <0xc000>;
95 d-cache-size = <0x8000>;
99 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno-r2.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A72_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
50 CPU_SLEEP_0: cpu-sleep-0 {
53 arm,psci-suspend-param = <0x0010000>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
63 arm,psci-suspend-param = <0x1010000>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
[all …]
/linux/include/sound/
H A Dacp63_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x0000000
13 #define ACP_DMA_CNTL_1 0x0000004
14 #define ACP_DMA_CNTL_2 0x0000008
15 #define ACP_DMA_CNTL_3 0x000000C
16 #define ACP_DMA_CNTL_4 0x0000010
17 #define ACP_DMA_CNTL_5 0x0000014
18 #define ACP_DMA_CNTL_6 0x0000018
19 #define ACP_DMA_CNTL_7 0x000001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
[all …]
/linux/drivers/video/fbdev/
H A Dffb.c64 #define FFB_SFB8R_VOFF 0x00000000
65 #define FFB_SFB8G_VOFF 0x00400000
66 #define FFB_SFB8B_VOFF 0x00800000
67 #define FFB_SFB8X_VOFF 0x00c00000
68 #define FFB_SFB32_VOFF 0x01000000
69 #define FFB_SFB64_VOFF 0x02000000
70 #define FFB_FBC_REGS_VOFF 0x04000000
71 #define FFB_BM_FBC_REGS_VOFF 0x04002000
72 #define FFB_DFB8R_VOFF 0x04004000
73 #define FFB_DFB8G_VOFF 0x04404000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
64 reg = <0x0 0x1>;
76 reg = <0x0 0x2>;
88 reg = <0x0 0x3>;
103 arm,psci-suspend-param = <0x0010000>;
147 opp-supported-hw = <0xf9 0xffff>;
[all …]
H A Drk3308.dtsi44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
72 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
109 cpu0_opp_table: opp-table-0 {
149 #clock-cells = <0>;
167 #clock-cells = <0>;
[all …]
H A Drk3328.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
62 reg = <0x0 0x1>;
69 i-cache-size = <0x8000>;
72 d-cache-size = <0x8000>;
81 reg = <0x0 0x2>;
88 i-cache-size = <0x8000>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
93 opp-supported-hw = <0xf>, <0xf>;
99 #clock-cells = <0>;
106 #clock-cells = <0>;
115 #phy-cells = <0>;
123 #phy-cells = <0>;
142 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]

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